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Displaying 1-9 out of 9 total
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
Found in: Computer Design, International Conference on
By Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
Issue Date:October 2005
pp. 411-416
<p>As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine ...
 
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
Found in: Quality Electronic Design, International Symposium on
By Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
Issue Date:March 2005
pp. 346-351
This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the import...
 
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Issue Date:March 2008
pp. 426-431
We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) ...
 
3D Integration for Introspection
Found in: IEEE Micro
By Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
Issue Date:January 2007
pp. 77-83
In today's complex processors, specialized profiling and introspection hardware would be incredibly beneficial to software developers, but most proposals for its addition would increase the cost of every die manufactured. Modular,
 
High-frequency mutual impedance extraction of VLSI interconnects in the presence of a multi-layer conducting substrate
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Kaustav Banerjee, Navin Srivastava, Roberto Suaya
Issue Date:March 2008
pp. 1-30
We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) ...
     
Introspective 3D chips
Found in: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS-XII)
By Banit Agrawal, Kaustav Banerjee, Navin Srivastava, Shashidhar Mysore, Sheng-Chih Lin, Tim Sherwood
Issue Date:October 2006
pp. 109-es
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexity of modern systems, software developers are increasingly dependent on specia...
     
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Banit Agrawal, Gian Luca Loi, Kaustav Banerjee, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood
Issue Date:July 2006
pp. 991-996
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can poten...
     
Are carbon nanotubes the future of VLSI interconnections?
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Kaustav Banerjee, Navin Srivastava
Issue Date:July 2006
pp. 809-814
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates tha...
     
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Kaustav Banerjee, Navin Srivastava, Sheng-Chih Lin
Issue Date:January 2006
pp. 223-230
Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This pa...
     
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