CS Store Search
Displaying 1-3 out of 3 total
Compiler-assisted, selective out-of-order commit
IEEE Computer Architecture Letters
By Nam Duong,A. V. Veidenbaum
Issue Date:January 2013
This paper proposes an out-of-order instruction commit mechanism using a novel compiler/architecture interface. The compiler creates instruction “blocks” guaranteeing some commit conditions and the processor uses the block information to commit certain ins...
Improving Cache Management Policies Using Dynamic Reuse Distances
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
By Nam Duong,Dali Zhao,Taesu Kim,Rosario Cammarota,Mateo Valero,Alexander V. Veidenbaum
Issue Date:December 2012
Cache management policies such as replacement, bypass, or shared cache partitioning have been relying on data reuse behavior to predict the future. This paper proposes a new way to use dynamic reuse distances to further improve such policies. A new replace...
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files
Application Specific Processors, Symposium on
By Nam Duong, Rakesh Kumar
Issue Date:July 2009
In this paper, we investigate Register Multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple ph...
Original Search Engine
Need a Web Account?
Become a Member
This site and all contents (unless otherwise noted) are Copyright ©2008, IEEE, Inc. All rights reserved.