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Displaying 1-12 out of 12 total
Towards a tool for implementing delay-free ECC in embedded memories
Found in: Computer Design, International Conference on
By Thierry Bonnoit,Michael Nicolaidis,Nacer-Eddine Zergainoh
Issue Date:October 2011
pp. 441-442
The reliability of modern Integrated Circuits is affected by nanometric scaling. In many modern designs embedded memories occupy the largest part of the die and are designed as tight as allowed by the process. So they are more prone to failures than other ...
 
Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems
Found in: Network Computing and Applications, IEEE International Symposium on
By Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis
Issue Date:July 2010
pp. 52-59
Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, as the Deep submicron technology fore- shadows highly defective chips era, fault-tolerant designs become compulsory. In particul...
 
Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip
Found in: On-Line Testing Symposium, IEEE International
By Gilles Bizot, Nacer-Eddine Zergainoh, Nichael Nicolaidis
Issue Date:June 2009
pp. 155
As technology scales, designing a massively parallel multi-cores system atop less reliable hardware architecture poses great challenges for researchers and designers. In this environment, ignoring variation effects when scheduling applications or when mana...
 
Buffer Size Reduction through Control-Flow Decomposition
Found in: Real-Time Computing Systems and Applications, International Workshop on
By Nacer-Eddine Zergainoh, Ahmed A. Jerraya, Kiyoung Choi
Issue Date:August 2007
pp. 183-190
Software synthesis from a data-flow model has been a very promising technique, especially for multimedia applications with contradicting requirements of high design complexity and fast time-to-market. In a dataflow model, buffer size is pessimistically det...
 
Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes
Found in: Rapid System Prototyping, IEEE International Workshop on
By Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed A. Jerraya
Issue Date:May 2007
pp. 195-201
Modeling a system with communicating concurrent processes is an effective way of exposing parallelism inherent in the application. When multiple processes are mapped to a processor, however, we have to serialize the execution of the processes. Such seriali...
 
Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Youssef Atat, Nacer-Eddine Zergainoh
Issue Date:March 2007
pp. 9-14
The rise of the abstraction level when designing the hardware (HW) and software (SW) parts of multiprocessor systems on chip (MPSoC) permits to master the growing complexity of these systems. However, it generates a huge gap between the concepts of system ...
 
Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems
Found in: IEEE Transactions on Software Engineering
By Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
Issue Date:September 2002
pp. 822-831
<p><b>Abstract</b>—This paper addresses performance estimation and architecture exploration issues within the context of hardware/software codesign. We introduce a new methodology to rapidly explore the large design space encountered in h...
 
Self-Recovering Parallel Applications in Multi-core Systems
Found in: Network Computing and Applications, IEEE International Symposium on
By Gilles Bizot,Dimiter Avresky,Fabien Chaix,Nacer-Eddine Zergainoh,Michael Nicolaidis
Issue Date:August 2011
pp. 51-58
In this paper, a Self-Recovering strategy, which is able to
 
Variability-aware task mapping strategies for many-cores processor chips
Found in: On-Line Testing Symposium, IEEE International
By F. Chaix,G. Bizot,M. Nicolaidis,Nacer-Eddine Zergainoh
Issue Date:July 2011
pp. 55-60
The advent of the Deep Submicron technology opens the way to many-cores processor chips. However, the variability and reliability of these processes poses new challenges. In particular, the mapping of applications will require specific strategies to levera...
 
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
Issue Date:March 2003
pp. 20132
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip communication network, communication interfaces of processor/IP/memory, on-chip...
 
Variability-aware and fault-tolerant self-adaptive applications for many-core chips
Found in: 2013 18th IEEE European Test Symposium (ETS)
By Gilles Bizot,Fabien Chaix,Nacer-Eddine Zergainoh,Michael Nicolaidis
Issue Date:May 2013
pp. 1
The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computin...
   
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor
Found in: European Test Symposium, IEEE
By Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh
Issue Date:May 2011
pp. 93-98
Soft errors have been emerged as an important reliability concern of modern ICs. In this work we have implemented an efficient error detection scheme in a low power DSP/MCU processor. Our scheme achieves high error detection efficiency at low hardware cost...
 
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