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Displaying 1-8 out of 8 total
Optical Interconnects for High-Performance Computing Systems
Found in: IEEE Micro
By Michael R.T. Tan,Moray McLaren,Norman P. Jouppi
Issue Date:January 2013
pp. 14-21
A first step toward advanced optical interconnect technologies is a data-center switch using a multibus optical backplane. This network switch replaces the electronic backplane and communications fabric application-specific integrated circuit (ASIC) with a...
 
CMOS nanophotonics for exascale systems
Found in: International Conference on Green Computing
By Moray McLaren
Issue Date:August 2010
pp. 535
A critical challenge on the path to exascale systems is the growing proportion of power consumed in interconnects. Optical communication can potentially reduce the energy per bit of communication at both the interchip and intrachip level. The cost of conve...
 
HyperX: topology, routing, and packaging of efficient large-scale networks
Found in: SC Conference
By Jung Ho Ahn, Nathan Binkert, Al Davis, Moray McLaren, Robert S. Schreiber
Issue Date:November 2009
pp. 1-11
In the push to achieve exascale performance, systems will grow to over 100,000 sockets, as growing cores-per-socket and improved single-core performance provide only part of the speedup needed. These systems will need affordable interconnect structures tha...
 
A High-Speed Optical Multidrop Bus for Computer Interconnections
Found in: IEEE Micro
By Michael R.T. Tan, Paul Rosenberg, Jong-Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Huei Pei Kuo, Joseph Straznicky, Norman P. Jouppi, Shih-Yuan Wang
Issue Date:July 2009
pp. 62-73
<p>Signal integrity constraints of high-speed electronics have made multidrop electrical buses infeasible. This high-speed alternative uses hollow metal waveguides and pellicle beam splitters that interconnect modules attached to the bus. With 1 mW o...
 
Corona: System Implications of Emerging Nanophotonic Technology
Found in: Computer Architecture, International Symposium on
By Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan Binkert, Raymond G. Beausoleil, Jung Ho Ahn
Issue Date:June 2008
pp. 153-164
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitu...
 
QsNetII: Defining High-Performance Network Design
Found in: IEEE Micro
By Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha
Issue Date:July 2005
pp. 34-47
QsNetII optimizes interprocessor communication in systems built from standard server building blocks. Its short-message processing unit permits fast injection of small messages, providing ultra-low latency and scalability to thousands of nodes.
 
The role of optics in future high radix switch design
Found in: Proceeding of the 38th annual international symposium on Computer architecture (ISCA '11)
By Al Davis, Jung Ho Ahn, Moray McLaren, Nathan Binkert, Naveen Muralimanohar, Norman P. Jouppi, Robert Schreiber
Issue Date:June 2011
pp. 437-448
For large-scale networks, high-radix switches reduce hop and switch count, which decreases latency and power. The ITRS projections for signal-pin count and per-pin bandwidth are nearly flat over the next decade, so increased radix in electronic switches wi...
     
HyperX: topology, routing, and packaging of efficient large-scale networks
Found in: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC '09)
By Al Davis, Jung Ho Ahn, Moray McLaren, Nathan Binkert, Robert S. Schreiber
Issue Date:November 2009
pp. 1-11
In the push to achieve exascale performance, systems will grow to over 100,000 sockets, as growing cores-per-socket and improved single-core performance provide only part of the speedup needed. These systems will need affordable interconnect structures tha...
     
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