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Displaying 1-14 out of 14 total
An OpenCL Runtime Library for Embedded Multi-Core Accelerator
Found in: 2012 IEEE 18th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012)
By Ryuichi Sakamoto,Mikiko Sato,Yusuke Koizumi,Hideharu Amano,Mitaro Namiki
Issue Date:August 2012
pp. 419-422
In recent years, improvements of energy efficiency and computational performance have become a major issue, because smartphones and tablets become popular. To implement high performance, multi-core accelerator consists of general purpose processors and acc...
 
Multithreaded Two-Phase I/O: Improving Collective MPI-IO Performance on a Lustre File System
Found in: 2014 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
By Yuichi Tsujita,Kazumi Yoshinaga,Atsushi Hori,Mikiko Sato,Mitaro Namiki,Yutaka Ishikawa
Issue Date:February 2014
pp. 232-235
ROMIO, a representative MPI-IO implementation, has been widely used in recent large-scale parallel computations. The two-phase I/O optimization scheme of ROMIO improves I/O performance for non-contiguous access patterns, however, this scheme still has room...
 
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
Found in: IEEE Micro
By Noriyuki Miura,Yusuke Koizumi,Yasuhiro Take,Hiroki Matsutani,Tadahiro Kuroda,Hideharu Amano,Ryuichi Sakamoto,Mitaro Namiki,Kimiyoshi Usami,Masaaki Kondo,Hiroshi Nakamura
Issue Date:November 2013
pp. 6-15
The authors developed a scalable heterogeneous multicore processor. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-offs between performance and energy consumption. The stacked chips i...
 
A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI
Found in: 2013 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
By Kazumi Yoshinaga,Yuichi Tsujita,Atsushi Hori,Mikiko Sato,Mitaro Namiki,Yutaka Ishikawa
Issue Date:February 2013
pp. 249-253
This paper describes a delegation based high throughput MPIcommunication mechanism under tough memory utilization constrains on a many-core oriented hybrid parallel computer. Towards the Exascale era, hybrid parallel computers consisting of many-core and m...
 
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips
Found in: IEEE Micro
By Nobuaki Ozaki,Yoshihiro Yasuda,Yoshiki Saito,Daisuke Ikebuchi,Masayuki Kimura,Hideharu Amano,Hiroshi Nakamura,Kimiyoshi Usami,Mitaro Namiki,Masaaki Kondo
Issue Date:November 2011
pp. 6-18
Cool Mega-Array (CMA) is an energy-efficient reconfigurable accelerator for battery-driven mobile devices. It has a large processing-element array without memory elements for mapping an application's data-flow graph, a simple programmable microcontroller f...
 
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator
Found in: IEEE Cool Chips
By Nobuaki Ozaki,Kimiyoshi Usami,Hideharu Amano,Mitaro Namiki,Hiroshi Nakamura,Masaaki Kondo
Issue Date:April 2011
pp. 1-3
SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricat...
 
Reducing instruction TLB's leakage power consumption for embedded processors
Found in: International Conference on Green Computing
By Zhao Lei, Hui Xu, Dasuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki
Issue Date:August 2010
pp. 477-484
This paper presents a leakage efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page following instructions tend to be fetched from the same page for a rather...
 
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression
Found in: VLSI Design, International Conference on
By Kimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Issue Date:January 2009
pp. 381-386
This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. I...
 
A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface
Found in: IEEE Micro
By Yusuke Koizumi,Noriyuki Miura,Eiichi Sasaki,Yasuhiro Take,Hiroki Matsutani,Tadahiro Kuroda,Hideharu Amano,Ryuichi Sakamoto,Mitaro Namiki,Kimiyoshi Usami,Masaaki Kondo,Hiroshi Nakamura
Issue Date:December 2013
pp. 1
A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-off between performance and energy consumption. The stacked chips interconne...
 
Impact of Dynamic Allocation of Physical Register Banks for an SMT Processor
Found in: Innovative Architecture for Future Generation High-Performance Processors and Systems, International Workshop on
By Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
Issue Date:January 2004
pp. 139-147
In an SMT processor, the increase of the register contexts of a thread requires a large number of physical registers. Moreover, a physical register file in an SMT processor requires more ports for the execution units, which cause significant growth of the ...
 
A design of hybrid operating system for a parallel computer with multi-core and many-core processors
Found in: Proceedings of the 2nd International Workshop on Runtime and Operating Systems for Supercomputers (ROSS '12)
By Atsushi Hori, Go Fukazawa, Kazumi Yoshinaga, Kiyohiko Nagamine, Mikiko Sato, Mitaro Namiki, Ryuichi Sakamoto, Yuichi Tsujita, Yutaka Ishikawa
Issue Date:June 2012
pp. 1-8
This paper describes the design of an operating system to manage the hybrid computer system architecture with multi-core and many-core processors for Exa-scale computing. In this study, a host operating system (Host OS) on a multi-core processor performs s...
     
Acceleration experiment of genetic computations for sudoku solution on multi-core processors
Found in: Proceedings of the 13th annual conference companion on Genetic and evolutionary computation (GECCO '11)
By Mikiko Sato, Mitaro Namiki, Yuji Sato
Issue Date:July 2011
pp. 823-824
We focus on parallel-processing effect for Sudoku-solving and we show that diversifying initial values can reduce the Sudoku solution time. In an experiment using the commercially available Intel Corei7 multi-core processor, we show that a correct solution...
     
Proposal of a multi-core processor architecture for effective evolutionary computation
Found in: Proceedings of the 12th annual conference on Genetic and evolutionary computation (GECCO '10)
By Mikiko Sato, Mitaro Namiki, Yuji Sato
Issue Date:July 2010
pp. 1321-1322
This paper describes proposing multi-core processor architectures from the viewpoint of evolutionary computation. We focus on local memory built into a multi-core processor and propose a specification that allows the contents of local memory in any core to...
     
A CS unplugged design pattern
Found in: Proceedings of the 40th ACM technical symposium on Computer science education (SIGCSE '09)
By Mitaro Namiki, Susumu Kanemune, Tim Bell, Tomohiro Nishida, Yasushi Kuno, Yukio Idosaka
Issue Date:March 2009
pp. 1-6
"Computer Science (CS) Unplugged" is an educational method for introducing non-specialists to concepts of CS through hands-on activities that don't require the use of a computer. Often the deeper concepts of CS have been considered as being too difficult f...
     
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