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Displaying 1-9 out of 9 total
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, Tina Wen, Srinivas Devadas
Issue Date:September 2009
pp. 181-190
Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-routing flows, but requires more complex hardware to determine and configure ne...
 
Optimal and Heuristic Application-Aware Oblivious Routing
Found in: IEEE Transactions on Computers
By Michel A. Kinsy,Myong Hyon Cho,Keun Sup Shim,Mieszko Lis,G. Edward Suh,Srinivas Devadas
Issue Date:January 2013
pp. 59-73
Conventional oblivious routing algorithms do not take into account resource requirements (e.g., bandwidth, latency) of various flows in a given application. As they are not aware of flow demands that are specific to the application, network resources can b...
 
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
Found in: Computer Design, International Conference on
By Omer Khan,Henry Hoffmann,Mieszko Lis,Farrukh Hijaz,Anant Agarwal,Srinivas Devadas
Issue Date:October 2011
pp. 411-418
This paper proposes an architecturally redundant cache-coherence architecture (ARCc) that combines the directory and shared-NUCA based coherence protocols to improve performance, energy and dependability. Both coherence mechanisms co-exist in the hardware ...
 
Memory coherence in the age of multicores
Found in: Computer Design, International Conference on
By Mieszko Lis,Keun Sup Shim,Myong Hyon Cho,Srinivas Devadas
Issue Date:October 2011
pp. 1-8
As we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts pla...
 
Scalable, accurate multicore simulation in the 1000-core era
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas
Issue Date:April 2011
pp. 175-185
We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving fun...
 
Static virtual channel allocation in oblivious routing
Found in: Networks-on-Chip, International Symposium on
By Keun Sup Shim, Myong Hyon Cho, Michel Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh, Srinivas Devadas
Issue Date:May 2009
pp. 38-43
Most virtual channel routers have multiple virtual channels to mitigate the effects of head-of-line blocking. When there are more flows than virtual channels at a link, packets or flows must compete for channels, either in a dynamic way at each link or by ...
 
Thread Migration Prediction for Distributed Shared Caches
Found in: IEEE Computer Architecture Letters
By Keun Sup Shim,Mieszko Lis,Omer Khan,Srinivas Devadas
Issue Date:January 2014
pp. 1-1
Chip-multiprocessors (CMPs) have become the mainstream parallel architecture in recent years; for scalability reasons, designs with high core counts tend towards tiled CMPs with physically distributed shared caches. This naturally leads to a Non-Uniform Ca...
 
Brief announcement: distributed shared memory based on computation migration
Found in: Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures (SPAA '11)
By Christopher W. Fletcher, Ilia Lebedev, Keun Sup Shim, Michel Kinsy, Mieszko Lis, Myong Hyon Cho, Omer Khan, Srinivas Devadas
Issue Date:June 2011
pp. 253-256
We consider the interactive model of recommender systems, in which users are asked about just a few of their preferences, and in return the system outputs an approximation of all their preferences. The measure of performance is the probe complexity of the ...
     
Path-based, randomized, oblivious, minimal routing
Found in: Proceedings of the 2nd International Workshop on Network on Chip Architectures (NoCArc '09)
By Keun Sup Shim, Michel Kinsy, Mieszko Lis, Myong Hyon Cho, Srinivas Devadas
Issue Date:December 2009
pp. 23-28
Path-based, Randomized, Oblivious, Minimal routing (PROM) is a family of oblivious, minimal, path-diverse routing algorithms especially suitable for Network-on-Chip applications with n x n mesh geometry. Rather than choosing among all possible paths at the...
     
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