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Displaying 1-6 out of 6 total
Accelerator Memory Reuse in the Dark Silicon Era
Found in: IEEE Computer Architecture Letters
By Emilio G. Cota,Paolo Mantovani,Michele Petracca,Mario R. Casu,Luca P. Carloni
Issue Date:January 2014
pp. 1-1
Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the opportu...
Photonic NoCs: System-Level Design Exploration
Found in: IEEE Micro
By Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni
Issue Date:July 2009
pp. 74-85
<p>Network-on-chip is a key enabling technology to address the challenges of interconnecting the increasing number of cores in emerging chip multiprocessors. By leveraging recent advances in the CMOS integration of photonic devices and the unique pro...
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
Found in: High-Performance Interconnects, Symposium on
By Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni
Issue Date:August 2008
pp. 31-40
The Network-on-Chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-on chip(SoC) and chip multiprocessors (CMP). In future high performance CMPs, howev...
netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems
Found in: Proceedings of the 50th Annual Design Automation Conference (DAC '13)
By Michele Petracca, YoungHoon Jung
Issue Date:May 2013
pp. 1-10
From a single SoC to a network of embedded devices communicating with a backend cloud-computing server, emerging classes of embedded systems feature an increasing number of heterogeneous components that operate concurrently in a distributed environment. As...
Virtual channels vs. multiple physical networks: a comparative analysis
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Luca Carloni, Michele Petracca, Nicola Concer, Young Jin Yoon
Issue Date:June 2010
pp. 162-165
Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoid deadlock and optimize the bandwidth of the physical channels in exchange fo...
Distributed flit-buffer flow control for networks-on-chip
Found in: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis (CODES/ISSS '08)
By Luca P. Carloni, Michele Petracca, Nicola Concer
Issue Date:October 2008
pp. 1001-1001
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure, the two techniques are easy to combine while offering complementary advantages:...