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Displaying 1-3 out of 3 total
Centip3De: A 64-Core, 3D Stacked Near-Threshold System
By Ronald G. Dreslinski,David Fick,Bharan Giridhar,Gyouho Kim,Sangwon Seo,Matthew Fojtik,Sudhir Satpathy,Yoonmyung Lee,Daeyeon Kim,Nurrachman Liu,Michael Wieckowski,Gregory Chen,Dennis Sylvester,David Blaauw,Trevor Mudge
Issue Date:March 2013
Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is...
A New Test Methodology For DNL Error In Flash ADC?s
Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala
Issue Date:October 2005
<p>A novel test methodology is presented for characterizing DNL error in Flash analog to digital converters. This test technique accurately measures the resistance of each resistor in the Flash ladder and in turn, characterizes the DNL of a given chi...
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing
Found in: Communications of the ACM
By Bharan Giridhar, David Fick, Dennis Sylvester, Gregory Chen, Matthew Fojtik, Ronald G. Dreslinski, Daeyeon Kim, David Blaauw, Gyouho Kim, Michael Wieckowski, Nurrachman Liu, Sangwon Seo, Sudhir Satpathy, Trevor Mudge, Yoonmyung Lee
Issue Date:November 2013
Process scaling has resulted in an exponential increase of the number of transistors available to designers. Meanwhile, global interconnect has not scaled nearly as well, because global wires scale only in one dimension instead of two, resulting in fewer, ...
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