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Displaying 1-8 out of 8 total
Accelerated Shift Registers for X-tolerant Test Data Compaction
Found in: European Test Symposium, IEEE
By Martin Hilscher, Michael Braun, Michael Richter, Andreas Leininger, Michael Gössel
Issue Date:May 2008
pp. 133-139
In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple i...
Concurrent checking with split-parity codes
Found in: On-Line Testing Symposium, IEEE International
By Michael Richter, Michael Goessel
Issue Date:June 2009
pp. 159-163
In this paper the design of error detection circuits for split-parity codes is investigated. In a split-parity code the linear parity bit is split into two nonlinear check bits. Split-parity codes, like parity codes, detect all odd errors with certainty; a...
New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability
Found in: On-Line Testing Symposium, IEEE International
By Michael Richter, Klaus Oberlaender, Michael Goessel
Issue Date:July 2008
pp. 37-42
This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrect...
High Performance Compaction for Test Responses with Many Unknowns
Found in: Asian Test Symposium
By Thomas Rabenalt, Michael Richter, Michael Goessel
Issue Date:December 2010
pp. 179-184
We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a single, 1-bit wide bit stream. A major contribution of this work is a new technique to efficient...
Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs
Found in: IEEE Transactions on Computers
By Michael Richter,Krishnendu Chakrabarty
Issue Date:March 2014
pp. 691-702
We present the first pin-count-aware optimization approach for test data delivery over a network-on-chip (NoC). Our approach addresses the key issue of optimal utilization of the limited I/O resources provided by automated test equipment (ATE) to keep test...
A dynamic programming solution for optimizing test delivery in multicore SOCs
Found in: 2012 IEEE International Test Conference (ITC)
By Mukesh Agrawal,Michael Richter,Krishnendu Chakrabarty
Issue Date:November 2012
pp. 1-10
We present a test-data delivery optimization algorithm for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. The proposed algorithm is the first to co-optimize the number of access poi...
Time Warp Simulation of Timed Petri Nets Sensitivity of Adaptive Methods
Found in: Petri Nets and Performance Models, IEEE International Workshop on
By Alois Ferscha, Michael Richter
Issue Date:June 1997
pp. 205
The unthrottled optimism underlying the Time Warp (TW) parallel simulation protocol can lead to excessive aggressiveness in memory consumption due to saving state histories, and waste of CPU cycles due to overoptimistically progressing simulations that eve...
Java based conservative distributed simulation
Found in: Proceedings of the 29th conference on Winter simulation (WSC '97)
By Alois Ferscha, Michael Richter
Issue Date:December 1997
pp. 381-388
This paper describes the CONVERSIM simulation language. CONVERSIM is a developmental general-purpose, discrete-event language which has been used in the classroom to introduce the use and operation of simulators prior to the introduction of languages such ...