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Displaying 1-5 out of 5 total
Dynamic code footprint optimization for the IBM Cell Broadband Engine
Found in: Multicore Software Engineering, ICSE Workshop on
By Tobias Werth, Tobias Flossmann, Michael Klemm, Dominic Schell, Ulrich Weigand, Michael Philippsen
Issue Date:May 2009
pp. 64-72
Multicore designers often add a small local memory close to each core to speed up access and to reduce off-chip IO. But this approach puts a burden on the programmer, the compiler, and the runtime system, since this memory lacks hardware support (cache log...
Reparallelization and Migration of OpenMP Programs
Found in: Cluster Computing and the Grid, IEEE International Symposium on
By Michael Klemm, Matthias Bezold, Stefan Gabriel, Ronald Veldema, Michael Philippsen
Issue Date:May 2007
pp. 529-540
Typical computational grid users target only a single cluster and have to estimate the runtime of their jobs. Job schedulers prefer short-running jobs to maintain a high system utilization. If the user underestimates the runtime, premature termination caus...
Computer Support for Teaching and Learning
Found in: Computer-Human Interaction, Australasian Conference on
By Michael Klemme
Issue Date:November 1996
pp. 0340
This paper describes some opportunities and prerequisites for the use of computers in education. To render electronic information systems useful, a high degree of integration has to be archieved. Hypermedia systems can serve as a basic integration platform...
Performance of a Structure-Detecting SpMV Using the CSR Matrix Representation
Found in: 2012 11th International Symposium on Parallel and Distributed Computing (ISPDC)
By Hans Pabst,Bev Bachmayer,Michael Klemm
Issue Date:June 2012
pp. 3-10
Sparse matrix-vector multiplication (SpMV) is an important building block for many scientific applications. Various formats exist to store and represent sparse matrices in the computer's memory. The compressed row storage format (CRS or CSR) is typically a...
From GPGPU to Many-Core: Nvidia Fermi and Intel Many Integrated Core Architecture
Found in: Computing in Science and Engineering
By Alexander Heinecke,Michael Klemm,Hans-Joachim Bungartz
Issue Date:March 2012
pp. 78-83
Comparing the architectures and performance levels of an Nvidia Fermi accelerator with an Intel MIC Architecture coprocessor demonstrates the benefit of the coprocessor for bringing highly parallel applications into, or even beyond, GPGPU performance regio...