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Displaying 1-12 out of 12 total
Concurrent checking with split-parity codes
Found in: On-Line Testing Symposium, IEEE International
By Michael Richter, Michael Goessel
Issue Date:June 2009
pp. 159-163
In this paper the design of error detection circuits for split-parity codes is investigated. In a split-parity code the linear parity bit is split into two nonlinear check bits. Split-parity codes, like parity codes, detect all odd errors with certainty; a...
 
New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability
Found in: On-Line Testing Symposium, IEEE International
By Michael Richter, Klaus Oberlaender, Michael Goessel
Issue Date:July 2008
pp. 37-42
This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrect...
 
High Performance Compaction for Test Responses with Many Unknowns
Found in: Asian Test Symposium
By Thomas Rabenalt, Michael Richter, Michael Goessel
Issue Date:December 2010
pp. 179-184
We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a single, 1-bit wide bit stream. A major contribution of this work is a new technique to efficient...
 
Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By Stefan Weidling,Egor S. Sogomonyan,Michael Goessel
Issue Date:September 2013
pp. 855-862
In this paper it is shown how the method of error correction of transient errors in a combinational circuit by use of error detection codes can be implemented for a sum-bit duplicated adder, thereby the outputs of the adder circuit are stored in fault-tole...
 
On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture
Found in: European Test Symposium, IEEE
By Frank Poehl, Jan Rzeha, Matthias Beck, Michael Goessel, Ralf Arnold, Peter Ossimitz
Issue Date:May 2006
pp. 239-246
Technology and product ramp up suffers increasingly from systematic production defects. Diagnosis of scan test fail data plays an important role in yield enhancement as diagnosis of scan fail data helps to understand and overcome systematic production defe...
 
Low Cost Concurrent Error Detection for the Advanced Encryption Standard
Found in: Test Conference, International
By Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Goessel
Issue Date:October 2004
pp. 1242-1248
We present a new low-cost concurrent checking method for the Advanced Encryption Standard (AES) encryption algorithm. In this method, the parity of the 128-bit input is determined and modified step-by-step into the parity of the 128-bit output according to...
 
Parity-Based Concurrent Error Detection in Symmetric Block Ciphers
Found in: Test Conference, International
By Ramesh Karri, Grigori Kuznetsov, Michael Goessel
Issue Date:October 2003
pp. 919
Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurrent error detection (CED) approach against such attacks on symmetric block ciph...
 
Code-Disjoint Circuits for Parity Circuits
Found in: Asian Test Symposium
By Hendrik Hartje, Michael Goessel, Egor S. Sogomonyan
Issue Date:November 1997
pp. 100
In this paper it is shown how a circuit, given as a net-list of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Car...
 
Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By Stefan Weidling,Egor S. Sogomonyan,Michael Goessel
Issue Date:September 2013
pp. 855-862
In this paper it is shown how the method of error correction of transient errors in a combinational circuit by use of error detection codes can be implemented for a sum-bit duplicated adder, thereby the outputs of the adder circuit are stored in fault-tole...
 
A new method for correcting time and soft errors in combinational circuits
Found in: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
By Egor S. Sogomonyan,Stefan Weidling,Michael Goessel
Issue Date:April 2013
pp. 283-286
In this paper a simple method for fault tolerance with respect to transient or soft errors in the combinational part of sequential circuits is investigated. The memory elements of the sequential circuits are fault-tolerant master-slave-flip-flops. For corr...
   
Masking of X-values by Use of a Hierarchically Configurable Register
Found in: European Test Symposium, IEEE
By Thomas Rabenalt, Michael Goessel, Andreas Leininger
Issue Date:May 2009
pp. 149-154
In this paper we consider the test of large circuits. Due to the increasing number of scan chains of industrial designs and due to the limited recourses of the ATE-equipment the compression ratio of the test responses increases. A second issue are undefine...
 
Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores
Found in: VLSI Design, International Conference on
By Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Goessel
Issue Date:January 2000
pp. 382
A structure-independent method for space compaction based on a new generic scheme is presented in this paper. The compactor compresses test responses of a circuit-under-test (CUT) to a single periodic data stream with guaranteed zero-aliasing, and can be d...
 
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