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Displaying 1-12 out of 12 total
The Kremlin Oracle for Sequential Code Parallelization
Found in: IEEE Micro
By Saturnino Garcia,Donghwan Jeon,Christopher Louie,Michael Bedford Taylor
Issue Date:July 2012
pp. 42-53
The Kremlin open-source tool helps programmers by automatically identifying regions in sequential programs that merit parallelization. Kremlin combines a novel dynamic program analysis, hierarchical critical-path analysis, with multicore processor models t...
Skadu: Efficient vector shadow memories for poly-scopic program analysis
Found in: 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
By Donghwan Jeon,Saturnino Garcia,Michael Bedford Taylor
Issue Date:February 2013
pp. 1-12
Shadow memory is a critical component of many dynamic program analysis frameworks with applications ranging from memory debugging to computer security. Most recent work has focused on optimizing the execution time of analyses that associate a single tag wi...
An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors
Found in: International Conference on Field Programmable Logic and Applications
By Jack Sampson,Manish Arora,Nathan Goulding-Hotta,Ganesh Venkatesh,Jonathan Babb,Vikram Bhatt,Steven Swanson,Michael Bedford Taylor
Issue Date:September 2011
pp. 24-29
As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduc...
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson
Issue Date:May 2011
pp. 210-213
This paper describes an architecture and FPGA synthesis tool chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scal...
Efficient complex operators for irregular codes
Found in: High-Performance Computer Architecture, International Symposium on
By Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor
Issue Date:February 2011
pp. 491-502
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Found in: Computer Architecture, International Symposium on
By Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, Anant Agarwal
Issue Date:June 2004
pp. 2
This paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existi...
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
Found in: IEEE Micro
By Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Jae-Wook Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, Ana
Issue Date:March 2002
pp. 25-35
<p>Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency, and cost effectiveness.</p>
Quality Time: A simple online technique for quantifying multicore execution efficiency
Found in: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
By Anshuman Gupta,Jack Sampson,Michael Bedford Taylor
Issue Date:March 2014
pp. 169-179
In order to increase utilization, multicore processors share memory resources among an increasing number of cores. This sharing leads to memory interference, which in turn leads to a non-uniform degradation in the execution of concurrent applications, even...
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures
Found in: High-Performance Computer Architecture, International Symposium on
By Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, Anant Agarwal
Issue Date:February 2003
pp. 341
The bypass paths and multiported register files in microprocessors serve as an implicit interconnect to communicate operand values among pipeline stages and multiple ALUs. Previous superscalar designs implemented this interconnect using centralized structu...
QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Michael Bedford Taylor, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Steven Swanson, Ganesh Venkatesh, Jack Sampson
Issue Date:December 2011
pp. 163-174
Transistor density continues to increase exponentially, but power dissipation per transistor is improving only slightly with each generation of Moore's law. Given the constant chip-level power budgets, this exponentially decreases the percentage of transis...
Kremlin: rethinking and rebooting gprof for the multicore age
Found in: Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation (PLDI '11)
By Christopher M. Louie, Donghwan Jeon, Michael Bedford Taylor, Saturnino Garcia
Issue Date:June 2011
pp. 123-128
Many recent parallelization tools lower the barrier for parallelizing a program, but overlook one of the first questions that a programmer needs to answer: which parts of the program should I spend time parallelizing? This paper examines Kremlin, an automa...
Conservation cores: reducing the energy of mature computations
Found in: Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10)
By Ganesh Venkatesh, Jack Sampson, Jose Lugo-Martinez, Michael Bedford Taylor, Nathan Goulding, Saturnino Garcia, Steven Swanson, Vladyslav Bryksin
Issue Date:March 2010
pp. 222-230
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. In this regime, specialized, energy-effi...