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Displaying 1-12 out of 12 total
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled
Issue Date:April 2008
pp. 437-440
Conventional power gating techniques for minimizing leakage currents introduce ground bounce noise during power mode transition. Here an analysis of ground bounce due to power mode transition in power gating structures is presented. An innovative power gat...
 
Possible Noise Failure Modes in Static and Dynamic Circuits
Found in: System-on-Chip for Real-Time Applications, International Workshop on
By Masud H. Chowdhury, Yehea I. Ismail
Issue Date:July 2004
pp. 123-126
This paper investigates possible failure modes in both dynamic and static CMOS digital circuits due to noise disturbance. In current VLSI circuits, where mixture of static and dynamic implementation is very common, it is important to identify possible nois...
 
Interconnect technique for sub-threshold circuits using negative capacitance effect
Found in: Circuits and Systems, Midwest Symposium on
By Md. Sajjad Rahaman, Masud H Chowdhury
Issue Date:August 2009
pp. 1122-1125
Global interconnects in deep-submicron (DSM) regime contribute a significant amount of power consumption and large propagation delay. As the global interconnect delay dictating the overall system performance, its variation also has larger impact on system ...
 
VSIB: A Sensor Bus Architecture for Smart-Sensor Network
Found in: Computer Science and Information Engineering, World Congress on
By Md. Sajjad Rahaman, Masud H. Chowdhury, Irfan Nasir, Lih-Tyng Hwang
Issue Date:April 2009
pp. 436-439
There has been a proliferation of real-time sensing application due to the recent technological improvements in small, inexpensive, low-power, and distributed “smart” sensor nodes capable of doing a small amount of data processing and storage. Sensor netwo...
 
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files
Found in: Dependable Systems and Networks, International Conference on
By Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
Issue Date:July 2005
pp. 770-779
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop error correction mechanisms at the architecture level. Utilizing this increased...
 
Realizable RLCK Circuit Crunching
Found in: Design Automation Conference
By Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
Issue Date:June 2003
pp. 226
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of extracted RLCK netlists by node elimin...
 
Analysis of Coupling Noise in Dynamic Circuit
Found in: System-on-Chip for Real-Time Applications, International Workshop on
By Masud H. Chowdhury, Yehea I. Ismail
Issue Date:July 2003
pp. 320
Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed f...
 
Compact model for carbon nanotubes interconnects using fourier series analysis
Found in: Circuits and Systems, Midwest Symposium on
By Suraj Subash, Md Sajjad Rahaman, Masud H Chowdhury
Issue Date:August 2009
pp. 1175-1178
In current literature various equivalent circuit models and reduction techniques have been demonstrated to study the behavior and performance of carbon nano tubes (CNTs). However, most of these methods are very complex and predominantly use SPICE/HSPICE si...
 
Fast bus waveform estimation at the presence of coupling noise
Found in: Proceedings of the 18th ACM Great Lakes symposium on VLSI (GLSVLSI '08)
By Jingye Xu, Masud H. Chowdhury, Pervez Khaled
Issue Date:May 2008
pp. 1-37
With the technology scaling and shrinking feature sizes, coupling noise has become one of the most critical concerns in today's interconnect-centric design, especially for long global buses. A very common consequence of coupling is that the output signal w...
     
Effects of coupling capacitance and inductance on delay uncertainty and clock skew
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Abinash Roy, Masud H. Chowdhury, Noha Mahmoud
Issue Date:June 2007
pp. 184-187
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated circuits has become very critical. In this paper, the effects of capacitive a...
     
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Abinash Roy, Jingye Xu, Masud H. Chowdhury
Issue Date:April 2007
pp. 1218-1223
This paper addresses the problem of interconnect pipelining from both power consumption and bit error rate (BER) point of view and tries to find the optimal solution for a given wire pipelining scheme in nanometer scale very large scale integration technol...
     
Realizable RLCK circuit crunching
Found in: Proceedings of the 40th conference on Design automation (DAC '03)
By Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
Issue Date:June 2003
pp. 226-231
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describes a method for realizable reduction of extracted RLCK netlists by node elimin...
     
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