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Displaying 1-23 out of 23 total
A Federated Simulation Environment for Hybrid Systems
Found in: Parallel and Distributed Simulation, Workshop on
By Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain
Issue Date:June 2007
pp. 198-210
Hybrid computing systems consisting of multiple platform types (e.g., general purpose processors, FPGAs etc.) are increasingly being used to achieve higher performance and lower costs than can be obtained with homogeneous systems (e.g., processor clusters)...
 
Hierarchical Discrete-Event Simulation on Hypercube Architectures
Found in: IEEE Micro
By Roger D. Chamberlain, Mark A. Franklin
Issue Date:July 1990
pp. 10-20
<p>The simulation of systems that include components at varying levels of abstraction is addressed. A performance model of a hierarchical discrete-event simulation algorithm running on a hypercube architecture is presented. The model allows the perfo...
 
Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Michael DeVore, Roger Chamberlain, George Engel, Joseph O'Sullivan, Mark Franklin
Issue Date:July 2002
pp. 391
The implementation of computational systems to perform challenging operations often involves balancing the performance specification, system throughput, and available system resources. For problems of automatic target recognition (ATR), these three quantit...
 
Speculative Computation: Overcoming Communication Delays
Found in: Parallel Processing, International Conference on
By Vasudha Govindan, Mark A. Franklin
Issue Date:August 1994
pp. 12-16
Communication latencies and delays are a major source of performance degradation in parallel computing systems. It is important to
 
Gemini: An Optical Interconnection Network for Parallel Processing
Found in: IEEE Transactions on Parallel and Distributed Systems
By Roger D. Chamberlain, Mark A. Franklin, Ch'ng Shi Baw
Issue Date:October 2002
pp. 1038-1055
<p><b>Abstract</b>—The <it>Gemini</it> interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightly-coupled multicomputer systems. It consists of a circuit-switched optical dat...
 
Evaluating the Performance of Photonic Interconnection Networks
Found in: Simulation Symposium, Annual
By Roger Chamberlain, Ch'ng Shi Baw, Mark Franklin, Christopher Hackmann, Praveen Krishnamurthy, Abhijit Mahajan, Michael Wrighton
Issue Date:April 2002
pp. 0209
This paper describes the design and use of the Interconnection Network Simulator (ICNS) framework. ICNS is a modular, object-oriented simulation system that has been developed to investigate performance issues in multiprocessor interconnection networks tha...
 
The Gemini Interconnect: Data Path Measurements and Performance Analysis
Found in: Parallel Interconnects, International Conference on
By Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin, Michael G. Wrighton
Issue Date:October 1999
pp. 21
The Gemini interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightly-coupled multi-computer systems. It consists of a circuit-switched optical data path in parallel with a packet-switched electrical cont...
 
Design of an Interconnection Network Using VLSI Photonics and Free-Space Optical Technologies
Found in: Parallel Interconnects, International Conference on
By Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin
Issue Date:October 1999
pp. 52
This paper presents the design and initial analysis of an optically interconnected multiprocessor based on the use of VCSELs (Vertical Cavity Surface Emitting Laser) and free-space optical interconnects. The design is oriented to applications where the per...
 
Performance Optimization of Self-Timed Circuits
Found in: Great Lakes Symposium on VLSI
By Mark A. Franklin, Prithvi Prabhu
Issue Date:February 1998
pp. 374
In this paper, we present methods for improving the performance of self-timed computation blocks. The Hybrid Completion method permits the design of a spectrum of completion circuits ranging from those based on pure bounded delays to those based on full co...
 
Bloom Filter Performance on Graphics Engines
Found in: Parallel Processing, International Conference on
By Lin Ma,Roger D. Chamberlain,Jeremy D. Buhler,Mark A. Franklin
Issue Date:September 2011
pp. 522-531
Bloom filters are a probabilistic technique for large-scale set membership tests. They exhibit no false negative test results but are susceptible to false positive results. They are well-suited to both large sets and large numbers of membership tests. We i...
 
Auto-Pipe: Streaming Applications on Architecturally Diverse Systems
Found in: Computer
By Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, James H. Buckley, Jeremy Buhler, Greg Galloway, Saurabh Gayen, Michael Hall, E.F. Berkley Shands, Naveen Singla
Issue Date:March 2010
pp. 42-49
No summary available.
 
Application development on hybrid systems
Found in: SC Conference
By Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, Jeremy Buhler, Saurabh Gayen, Patrick Crowley, James H. Buckley
Issue Date:November 2007
pp. 1-10
Hybrid systems consisting of a multitude of different computing device types are interesting targets for high-performance applications. Chip multiprocessors, FPGAs, DSPs, and GPUs can be readily put together into a hybrid system; however, it is not at all ...
 
Performance Models for Network Processor Design
Found in: IEEE Transactions on Parallel and Distributed Systems
By Tilman Wolf, Mark A. Franklin
Issue Date:June 2006
pp. 548-561
<p><b>Abstract</b>—To provide a variety of new and advanced communications services, computer networks are required to perform increasingly complex packet processing. This processing typically takes place on network routers and their asso...
 
An Architecture for Fast Processing of Large Unstructured Data Sets
Found in: Computer Design, International Conference on
By Mark Franklin, Roger Chamberlain, Michael Henrichs, Berkley Shands, Jason White
Issue Date:October 2004
pp. 280-287
This paper presents a general system architecture tailored to performing searching, filtering, compression, encryption, and other operations on unstructured data streaming from a disk system. The system achieves high performance on such applications by pro...
 
Biosequence Similarity Search on the Mercury System
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Praveen Krishnamurthy, Jeremy Buhler, Roger Chamberlain, Mark Franklin, Kwame Gyang, Joseph Lancaster
Issue Date:September 2004
pp. 365-375
Biosequence similarity search is an important application in modern molecular biology. Search algorithms aim to identify sets of sequences whose extensional similarity suggests a common evolutionary origin or function. The most widely used similarity searc...
 
Dynamic Reconfiguration of an Optical Interconnect
Found in: Simulation Symposium, Annual
By Praveen Krishnamurthy, Mark Franklin, Roger Chamberlain
Issue Date:April 2003
pp. 89
The advent of optical technology that can feasibly support extremely high bandwidth chip-to-chip communication raises a host of architectural questions in the design of digital systems. Terabit per second (and higher) bandwidths have not previously been av...
 
Optical Network Reconfiguration for Signal Processing Applications
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Roger Chamberlain, Mark Franklin, Praveen Krishnamurthy
Issue Date:July 2002
pp. 344
This paper considers a class of embedded signal processing applications.To achieve real-time performance these applications must be executed on a parallel processor.The paper focuses on the multiring optical interconnection network used in the system and s...
 
Fair Scheduling in an Optical Interconnection Network
Found in: Modeling, Analysis, and Simulation of Computer Systems, International Symposium on
By Ch'ng Shi Baw, Roger D. Chamberlain, Mark A. Franklin
Issue Date:March 1999
pp. 56
Existing fair scheduling schemes have focused primarily on scheduling multiple flows to a single output. The limited work that has focused on scheduling multiple flows to multiple outputs has assumed a non-blocking, slotted-time, packet-based network with ...
 
Application Load Imbalance on Parallel Processors
Found in: Parallel Processing Symposium, International
By Vasudha Govindan, Mark Franklin
Issue Date:April 1996
pp. 836
This paper addresses the issue of dynamic load imbalance in a class of synchronous iterative applications, and develops a model to represent their workload dynamics. Such models of application load dynamics help in more accurate performance prediction and ...
 
Performance Comparison of Parallel Finite Element and Monte Carlo Methods in Optical Tomography
Found in: Parallel Processing Workshops, International Conference on
By Stefan Hendrata, Mark A. Franklin
Issue Date:September 2001
pp. 0051
Abstract: Optical tomography is a promising medical imaging method which uses visible light. For optical tomography, the ability to solve the
 
One-dimensional optimization on multiprocessor systems
Found in: IEEE Transactions on Computers
By Mark A. Franklin,Norman L. Soong
Issue Date:January 1981
pp. 61-66
This paper presents a straightforward approach to determining how best to utilize an MIMD multiprocessor in the solution of one-dimensional optimization problems involving continuous unimodal functions and nongradient search techniques. A methodology is pr...
   
Application development on hybrid systems
Found in: Proceedings of the 2007 ACM/IEEE conference on Supercomputing (SC '07)
By Eric J. Tyson, James H. Buckley, Jeremy Buhler, Mark A. Franklin, Patrick Crowley, Roger D. Chamberlain, Saurabh Gayen
Issue Date:November 2007
pp. 24-31
Hybrid systems consisting of a multitude of different computing device types are interesting targets for high-performance applications. Chip multiprocessors, FPGAs, DSPs, and GPUs can be readily put together into a hybrid system; however, it is not at all ...
     
Performance/area efficiency in chip multiprocessors with micro-caches
Found in: Proceedings of the 4th international conference on Computing frontiers (CF '07)
By Mark A. Franklin, Michela Becchi, Patrick J. Crowley
Issue Date:May 2007
pp. 247-258
This paper proposes the use of very small instruction caches, called micro-caches (μ-caches), consisting of tens to hundreds of bytes, at the bottom of the instruction delivery hierarchy in chip-multiprocessors (CMP). Multi-core architectures place a ...
     
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