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Displaying 1-23 out of 23 total
Radiation effects on programmable analog devices and mitigation techniques
Found in: On-Line Testing Symposium, IEEE International
By Tiago R. Balen, Marcelo Lubaszewski
Issue Date:July 2010
pp. 136
Radiation effects on electronic systems have been widely investigated since the first evidences that radioactivity can disturb electronic devices [1]. The main sources of natural space radiation are the Van Allen belts, solar activity, and galactic cosmic ...
 
Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Marcelo Lubaszewski
Issue Date:October 2009
pp. 224
No summary available.
 
Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults
Found in: On-Line Testing Symposium, IEEE International
By Caroline Concatto, Pedro Almeida, Fernanda Kastensmidt, Erika Cota, Marcelo Lubaszewski, Marcos Herve
Issue Date:June 2009
pp. 61-66
We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for th...
 
Diagnosis of interconnect shorts in mesh NoCs
Found in: Networks-on-Chip, International Symposium on
By Marcos Herve, Erika Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski
Issue Date:May 2009
pp. 256-265
We propose a method to diagnose interconnect short-circuit faults in mesh 7oCs. The fault model comprises all shorts between any two wires of a defined 7oC neighborhood. Test sequences are applied in 7oC functional mode. Experimental results show that 93% ...
 
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism
Found in: VLSI Test Symposium, IEEE
By Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes
Issue Date:May 2007
pp. 435-440
This paper presents new DfT modules required to use networks-on- chip as test access mechanism. We demonstrate that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. networks without complex services. The DfT module...
 
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays
Found in: VLSI Test Symposium, IEEE
By Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
Issue Date:May 2005
pp. 389-394
The test of Field Programmable Analog Arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local...
 
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Alexandre M. Amory, Marcelo Lubaszewski, Fernando G. Moraes, Edson I. Moreno
Issue Date:March 2005
pp. 62-63
The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom logic. Considering ...
   
Power-aware NoC Reuse on the Testing of Core-based Systems
Found in: Test Conference, International
By Érika Cota, Luigi Carro, Flávio Wagner, Marcelo Lubaszewski
Issue Date:October 2003
pp. 612
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider po...
 
SIFU! - A Didactic Stuck-at Fault Simulator
Found in: Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on
By Vinícius P. Correia, Marcelo Lubaszewski, André I. Reis
Issue Date:June 2003
pp. 93
This paper presents a didactic simulator for stuck-at (sa) faults on logic circuits. The tool has a set of features that helps to understand the concepts of single and multiple stuck-at faults, being these faults testable or not, and how to generate test v...
   
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus
Found in: VLSI Test Symposium, IEEE
By Jose Vicente Calvano, Vladimir Castro Alves, Antonio C. Mesquita, Marcelo Lubaszewski
Issue Date:May 2002
pp. 0201
This work presents a design for test method for continuous time active filters of any order, using the IEEE 1149.4 as its backbone structure. The method relies on the synthesis of filter transfer functions using partial fraction extraction. Transfer functi...
 
A BIST Procedure for Analog Mixers in Software Radio
Found in: Integrated Circuit Design and System Design, Symposium on
By André C. Nácul, Luigi Carro, Daniel Janner, Marcelo Lubaszewski
Issue Date:September 2001
pp. 0103
Abstract: This work describes a technique for testing mixers with digital adaptive filters. RF circuits are widely used on data transmission applications, such as wireless communication, radio and portable phone systems. However, traditional analog bist co...
 
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations
Found in: VLSI Test Symposium, IEEE
By José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski
Issue Date:May 2000
pp. 319
This work proposes a new BIST scheme for 2nd order Butterworth, Chebyshev and Bessel filter approximations, using the transient analysis of simple input test vectors. A functional approach for fault modeling in 2nd order filters is presented and the Transi...
 
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Érika Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
Issue Date:March 2000
pp. 226
The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8th analog line...
 
Implementing a Self-Testing 8051 Microprocessor
Found in: Integrated Circuit Design and System Design, Symposium on
By Erika F. Cota, Margrit R. Krug, Marcelo Lubaszewski, Luigi Carro, Altamiro A. Susin
Issue Date:October 1999
pp. 0202
This work presents the preliminary results obtained for the high level implementation of a self-testing 8051 microprocessor. From an existing VHDL description of the microprocessor, six main blocks were identified: a state generation block, a control unit,...
 
Fault Detection in Systems with 2 nd Order Dynamics using Transient Analysis
Found in: Integrated Circuit Design and System Design, Symposium on
By José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski
Issue Date:October 1999
pp. 0110
This work proposes a transient analysis method for fault detection in systems with 2nd order dynamics using a functional fault model. The approach consider the system pole-zero configuration as its main characteristic and its correspondence with the peak t...
 
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Erika F. Cota, Luigi Carro, Marcelo Lubaszewski
Issue Date:March 1999
pp. 184
This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behavior in a first step, and comparing this behavior against the output of the circuit under ...
 
A Reliable Fail-Safe System
Found in: IEEE Transactions on Computers
By Marcelo Lubaszewski, Bernard Courtois
Issue Date:February 1998
pp. 236-241
<p><b>Abstract</b>—This paper describes a fault-tolerant system that is based on two replicas of a self-checking module and on an error-masking interface. The main contributions of this work rely on the fail-safe/strongly-fail-safe design...
 
Microsystems Testing: an Approach and Open Problems
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Marcelo Lubaszewski, Erika F. Cota, Bernard Courtois
Issue Date:February 1998
pp. 524
In this work a Computer-Aided Testing (CAT) tool is proposed that brings a systematic way of dealing with testing problems in emerging microsystems. Experiments with case-studies illustrate the techniques and tools embedded in the CAT environment. Some of ...
 
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC
Found in: 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By Lucas Tambara,Fernanda Kastensmidt,Paolo Rech,Tiago Balen,Marcelo Lubaszewski
Issue Date:August 2013
pp. 188-193
This paper describes a neutron-induced single event effect test in analog-to-digital converters of a Microsemi's programmable commercial mixed-signal system-on-chip. The main objective is to investigate the reliability of the charge redistribution successi...
   
ABILBO: Analog BuILt-in Block Observer
Found in: Computer-Aided Design, International Conference on
By Marcelo Lubaszewski, Leandro Pulz, Salvador Mir
Issue Date:November 1996
pp. 600
This paper presents a novel multifunctional test structure called Analog BuILt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage...
 
Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits
Found in: European Design and Test Conference
By Salvador Mir, Bernard Courtois, Marcelo Lubaszewski, Vladimir Kolarik
Issue Date:March 1996
pp. 254
A fault-based multifrequency test generation and fault diagnosis procedure is proposed in this work. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and maximal di...
 
Reducing test time with processor reuse in network-on-chip based systems
Found in: Proceedings of the 17th symposium on Integrated circuits and system design (SBCCI '04)
By Erika Cota, Alexandre M. Amory, Fernando G. Moraes, Marcelo Lubaszewski
Issue Date:September 2004
pp. 111-116
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is eva...
     
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
Found in: Proceedings of the 17th symposium on Integrated circuits and system design (SBCCI '04)
By Antonio Andrade, Erika Cota, Marcelo Lubaszewski
Issue Date:September 2004
pp. 105-110
Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years. However, current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the who...
     
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