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Displaying 1-7 out of 7 total
Redefining the Role of the CPU in the Era of CPU-GPU Integration
By Manish Arora,Siddhartha Nath,Subhra Mazumdar,Scott B. Baden,Dean M. Tullsen
Issue Date:November 2012
In an integrated CPU-GPU system, the CPU executes code that is profoundly different than in past CPU-only environments. This new code's characteristics should drive future CPU design and architecture. Post-GPU code has lower instruction-level parallelism, ...
An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors
International Conference on Field Programmable Logic and Applications
By Jack Sampson,Manish Arora,Nathan Goulding-Hotta,Ganesh Venkatesh,Jonathan Babb,Vikram Bhatt,Steven Swanson,Michael Bedford Taylor
Issue Date:September 2011
As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduc...
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson
Issue Date:May 2011
This paper describes an architecture and FPGA synthesis tool chain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scal...
A De-Centralized Scheduling and Load Balancing Algorithm for Heterogeneous Grid Environments
Parallel Processing Workshops, International Conference on
By Manish Arora, Sajal K. Das, Rupak Biswas
Issue Date:August 2002
In the past two decades, numerous scheduling and load balancing techniques have been proposed for locally distributed multiprocessor systems. However, they all suffer from significant deficiencies when extended to a Grid environment: some use a centralized...
Resistive Computation: A Critique
IEEE Computer Architecture Letters
By Hamid Mahmoodi,Sridevi Lakshmipuram,Manish Arora,Yashar Asgarieh,Houman Homayoun,Bill Lin,Dean M. Tullsen
Issue Date:August 2013
Resistive Computation  replaces conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based Look-Up Tables (LUTs). It has been proposed for tackling the power wall. Spin Transfer Torque RAM (STTRAM) is an emerging CMOS compatible non-volatile memo...
Coordinated energy management in heterogeneous processors
Found in: Proceedings of SC13: International Conference for High Performance Computing, Networking, Storage and Analysis (SC '13)
By Indrani Paul, Manish Arora, Sudhakar Yalamanchili, Vignesh Ravi, Srilatha Manne
Issue Date:November 2013
This paper examines energy management in a heterogeneous processor consisting of an integrated CPU-GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements ...
Cooperative boosting: needy versus greedy power management
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Indrani Paul, Manish Arora, Srilatha Manne, Sudhakar Yalamanchili, W. Lloyd Bircher
Issue Date:June 2013
This paper examines the interaction between thermal management techniques and power boosting in a state-of-the-art heterogeneous processor consisting of a set of CPU and GPU cores. We show that for classes of applications that utilize both the CPU and the ...
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