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Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test
Found in: On-Line Testing Symposium, IEEE International
By Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji
Issue Date:June 2009
pp. 237-242
Periodic testing of electronic devices on the field during application execution is becoming increasingly important. In addition, some of these applications are embedded and real-time, requiring the system to be operational for extended periods. In such ap...
 
Efficient scan-based BIST scheme for low power testing of VLSI chips
Found in: Proceedings of the 2006 international symposium on Low power electronics and design (ISLPED '06)
By Malav Shah
Issue Date:October 2006
pp. 376-381
It is seen that power dissipation during test mode is quite high compared to that during the functional mode of operation of a digital circuit. This may lead to damage of certain chips only because they are tested, leading to unnecessary loss of yield. Thi...
     
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