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Displaying 1-4 out of 4 total
Programmable DDRx Controllers
Found in: IEEE Micro
By Mahdi Nazm Bojnordi,Engin Ipek
Issue Date:May 2013
pp. 106-115
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatil...
 
A programmable memory controller for the DDRx interfacing standards
Found in: ACM Transactions on Computer Systems (TOCS)
By Mahdi Nazm Bojnordi, Engin Ipek
Issue Date:December 2013
pp. 1-31
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatil...
     
DESC: energy-efficient data exchange using synchronized counters
Found in: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46)
By Engin Ipek, Mahdi Nazm Bojnordi
Issue Date:December 2013
pp. 234-246
Increasing cache sizes in modern microprocessors require long wires to connect cache arrays to processor cores. As a result, the last-level cache (LLC) has become a major contributor to processor energy, necessitating techniques to increase the energy effi...
     
PARDIS: a programmable memory controller for the DDRx interfacing standards
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Engin Ipek, Mahdi Nazm Bojnordi
Issue Date:June 2012
pp. 13-24
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatil...
     
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