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Displaying 1-11 out of 11 total
FTSPM: A Fault-Tolerant ScratchPad Memory
Found in: 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
By Amir Mahdi Hosseini Monazzah,Hamed Farbeh,Seyed Ghassem Miremadi,Mahdi Fazeli,Hossein Asadi
Issue Date:June 2013
pp. 1-10
ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integr...
Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors
Found in: European Dependable Computing Conference
By Hamed Farbeh,Mahdi Fazeli,Faramarz Khosravi,Seyed Ghassem Miremadi
Issue Date:May 2012
pp. 218-226
Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories a...
Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors
Found in: Embedded and Ubiquitous Computing, IEEE/IFIP International Conference on
By Faramarz Khosravi,Hamed Farbeh,Mahdi Fazeli,Seyed Ghassem Miremadi
Issue Date:October 2011
pp. 114-119
This paper proposes an efficient concurrent error detection method using control flow checking for embedded processors. The proposed method is based on the co-operation of two hardware modules: 1) an on-chip hardware component to detect branch instructions...
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits
Found in: Digital Systems Design, Euromicro Symposium on
By Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori
Issue Date:September 2010
pp. 797-800
In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an er...
A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design
Found in: Dependable Systems and Networks, International Conference on
By Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Seyed Nematollah Ahmadian
Issue Date:July 2010
pp. 131-140
In this paper, we propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates, flip-flops, and paths of a circuit. Using such information, designers can selectively protect the vulnerable parts...
A Power Efficient Approach to Fault-Tolerant Register File Design
Found in: VLSI Design, International Conference on
By Mojtaba Amiri-Kamalabad, Seyed Ghassem Miremadi, Mahdi Fazeli
Issue Date:January 2008
pp. 21-26
Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault- tolerant techniques used in the register file of pr...
A Software-Based Error Detection Technique Using Encoded Signatures
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli
Issue Date:October 2006
pp. 389-400
In this Paper, a software-based control flow checking technique called SWTES (Softwarebased error detection Technique using Encoded Signatures) is presented and evaluated. This technique is processor independent and can be applied to any kind of processors...
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi
Issue Date:October 2005
pp. 266-274
<p>This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerP...
Coding Last Level STT-RAM Cache For High Endurance And Low Power
Found in: IEEE Computer Architecture Letters
By Sadegh Yazdanshenas,Mahsa Ranjbar,Mahdi Fazeli,Ahmad Patooghy
Issue Date:May 2013
pp. 1
STT-RAM technology has recently emerged as one of the most promising memory technologies. However, it&amp;#8217;s major problems, limited write endurance and high write energy, are still preventing it from being used as a drop-in replacement of SRAM ca...
A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Mahdi Fazeli, Seyed Ghassem Miremadi
Issue Date:October 2008
pp. 193-201
In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (Single Event Transient and Upset Robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element t...
FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption
Found in: Availability, Reliability and Security, International Conference on
By Navid Farazmand, Mahdi Fazeli, Seyyed Ghasem Miremadi
Issue Date:March 2008
pp. 33-38
This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs) without program interruption. The proposed technique is based on the modification of application software and minor changes in the underlying hardware. To dem...