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Displaying 1-15 out of 15 total
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
Found in: VLSI Test Symposium, IEEE
By M.B. Santos, F.M. Gongalves, I.C. Teixeira, J.P. Teixeira
Issue Date:April 1999
pp. 326
No summary available.
 
DFT and Probabilistic Testability Analysis at RTL
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By J.M. Fernandes, M.B. Santos, A.L. Oliveira, J.C. Teixeira
Issue Date:November 2006
pp. 41-47
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using three different approaches, an exact one, an approximated one that ignores the corre...
 
Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage
Found in: Design and Diagnostics of Electronic Circuits and Systems
By F. Guerreiro, J. Semiao, A. Pierce, M.B. Santos, I.M. Teixeira
Issue Date:April 2006
pp. 277-282
No summary available.
 
Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test
Found in: 11th IEEE International On-Line Testing Symposium
By M. Rodriguez-Irago,J.J. Rodriguez Andina,F. Vargas,M.B. Santos,I.C. Teixeira,J.P. Teixeira
Issue Date:May 2014
pp. 281,282,283,284,285,286
Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-V/sub DD/ test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulat...
 
Probabilistic Testability Analysis and DFT Methods at RTL
Found in: 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
By J.M. Fernandes,M.B. Santos,A.L. Oliveira,J.C. Teixeira
Issue Date:August 2013
pp. 214-215
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using an approach that takes into account correlations within pre-defined groups formed ba...
 
Built-in aging monitoring for safety-critical applications
Found in: On-Line Testing Symposium, IEEE International
By J.C. Vazquez, V. Champac, A.M. Ziesemer, R. Reis, I.C. Teixeira, M.B. Santos, J.P. Teixeira
Issue Date:June 2009
pp. 9-14
Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasi...
 
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Control
Found in: On-Line Testing Workshop, IEEE International
By F.M. Gonçalves, M.B. Santos, I.C. Teixeira, J. P. Teixeira
Issue Date:July 2001
pp. 0197
Abstract: The purpose of this paper is to present a methodology and tools for the design and test of a EN298 compliant ASIC chip for safety-critical gas burner control. Safe operation, as far as the critical variable is concerned, is guaranteed in the pres...
 
Quality of Electronic Design: From Architectural Level to Test Coverage
Found in: Quality Electronic Design, International Symposium on
By O.P. Dias, J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:March 2000
pp. 197
The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, e...
 
From System Level to Defect-Oriented Test: A Case Study
Found in: European Test Workshop, IEEE
By J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:September 1999
pp. 136
The purpose of this paper is to demonstrate the usefulness of a recently proposed Object-Oriented (OO) based methodology and tools (SysObj and Test-Adder) when applied in the design of testable hardware modules (eventually used as embedded cores in SOCs). ...
 
Defect-Oriented Test Quality Assessment using Fault Sampling and Simulation
Found in: Test Conference, International
By F.M. Gonçalves, M.B. Santos, I.C. Teixeira, J. P. Teixeira
Issue Date:October 1998
pp. 35
The purpose of this paper is to present a novel methodology for the estimation of VLSI products Defect Level, or reject rates, in the IC design environment. A new Defect-Oriented (DO) fault extraction and stratified sampling technique, implemented in an ex...
 
Test preparation for high coverage of physical defects in CMOS digital ICs
Found in: VLSI Test Symposium, IEEE
By M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Issue Date:May 1995
pp. 0330
Abstract: In this paper, a novel methodology for test preparation of digital ICs, aiming at high defect coverage and affordable computational effort, is proposed. A method is presented to heuristically generate a list of pseudo realistic (PSE) faults, at g...
 
Test preparation methodology for high coverage of physical defects in CMOS digital ICs
Found in: European Design and Test Conference
By M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Issue Date:March 1995
pp. 604
The constant increase of IC circuit complexity and quality requirements make high quality testing a difficult challenge. In this work, a methodology for test preparation leading to high physical defect coverage is proposed. Two new software tools are prese...
   
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By J. Semião, J. Freijedo, J.J. Rodríguez-Andina, F. Vargas, M.B. Santos, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2007
pp. 167-172
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (VDD) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional ...
 
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST
Found in: Test Conference, International
By M.B. Santos, I.C. Teixeira, J.P. Teixeira, S. Manich, R. Rodriquez, J. Figueras
Issue Date:October 2002
pp. 814
While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudo-random based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste ...
 
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Found in: European Test Workshop, IEEE
By M.B. Santos, F.M. Gonçalves, I.C. Teixeira, J.P. Teixeira
Issue Date:June 2001
pp. 99
The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability M...
 
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