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Displaying 1-50 out of 134 total
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:October 2005
pp. 445-453
<p>Software Implemented Hardware Fault Tolerance (SIHFT) techniques are able to detect most of the transient and permanent faults during the usual system operations. However, these techniques are not capable to detect some transient faults affecting ...
 
A Hybrid Approach to Fault Detection and Correction in SoCs
Found in: On-Line Testing Symposium, IEEE International
By P. Bernardi, L. Bolzani, M. Sonza Reorda
Issue Date:July 2007
pp. 107-112
The reliability of Systems-on-Chip (SoCs) is very important with respect to their use in different types of critical applications. Several fault tolerance techniques have been proposed to improve their fault detection and correction capabilities. These app...
 
Efficient Estimation of SEU Effects in SRAM-Based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By M. Sonza Reorda, L. Sterpone, M. Violante
Issue Date:July 2005
pp. 54-59
SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to Single Event Upsets (SEUs) and particular concerns arise from ...
 
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By E. Sánchez, M. Sonza Reorda, G. Squillero
Issue Date:October 2005
pp. 494-504
<p>In software-based self-test (SBST) a microprocessor executes a set of test programs devised for detecting the highest possible percentage of faults. The main advantages of this approach are its high defect fault coverage (being performed at-speed)...
 
On the Automation of the Test Flow of Complex SoCs
Found in: VLSI Test Symposium, IEEE
By D. Appello, V. Tancorre, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
Issue Date:May 2006
pp. 166-171
Modern Systems-on-Chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires to take fast decisions in the selection of structures and strategies at different stages of the design flow: early computation...
 
Integrating BIST Techniques for On-Line SoC Testing
Found in: On-Line Testing Symposium, IEEE International
By A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
Issue Date:July 2005
pp. 235-240
Today?s complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly ...
 
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sánchez, M. Sonza Reorda
Issue Date:September 2007
pp. 291-302
<p>In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of t...
 
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
Found in: On-Line Testing Symposium, IEEE International
By L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
Issue Date:July 2007
pp. 265-270
Test of peripheral modules has not yet been deeply investigated by the research community. When embedded in a system on a chip, peripheral cores introduce new issues for post-production testing. A peripheral core embedded in a SoC requires a test set able ...
 
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis
Found in: Asian Test Symposium
By D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda
Issue Date:November 2001
pp. 97
This paper deals with the diagnosis of faulty embedded RAMs and outlines the solution which is currently under evaluation within STMicroelectronics. The proposed solution exploits a BIST module implementing a March algorithm, defines a wrapper allowing its...
 
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:October 2001
pp. 0250
In this paper we propose a FPGA-based system to speed-up Fault Injection campaigns for the evaluation of the fault-tolerant capabilities of VLSI circuits. An environment is described, relying on FPGA-based emulation of the circuit. Suitable techniques are ...
 
Online hardening of programs against SEUs and SETs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By C. A. L. Lisbôa, L. Carro, M. Sonza Reorda, M. Violante
Issue Date:October 2006
pp. 280-290
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (S...
 
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core
Found in: Dependable Systems and Networks, International Conference on
By P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
Issue Date:July 2005
pp. 50-58
In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems? dependability more difficult than ever. In this paper we present a new approach to d...
 
Soft-Error Detection Using Control Flow Assertions
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:November 2003
pp. 581
Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In this paper, a software-based approach for developing safety-critical applications is analyzed. The technique is based on the introduction of addit...
 
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
Found in: Asian Test Symposium
By F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:November 1997
pp. 68
The constantly increasing circuit size makes the sequential ATPG problem a challenging area, even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation o...
 
Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores
Found in: On-Line Testing Symposium, IEEE International
By M. Grosso, M. Sonza Reorda
Issue Date:June 2009
pp. 95-100
Strategies based on periodic Software-Based Self-Test (SBST) represent an effective and cost-efficient solution for the detection of faults in low-cost embedded systems that do not require immediate recognition of error conditions. Today's integrated syste...
 
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores
Found in: Test Conference, International
By D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
Issue Date:October 2003
pp. 379
This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Exper...
 
An RT-level fault model with high gate level correlation
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
Issue Date:November 2000
pp. 3
With the advent of new RT-level design and test flows, new tools are needed to migrate at the RT-level the activities of fault simulation testability analysis, and test pattern generation. This paper focuses on fault simulation at the RT-level, and aims at...
 
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By F. Lima Kastensmidt, L. Sterpone, L. Carro, M. Sonza Reorda
Issue Date:March 2005
pp. 1290-1295
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing f...
 
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
Found in: Design, Automation and Test in Europe Conference and Exhibition
By F. Corno, M. Sonza Reorda, G. Squillero, A. Manzone, A. Pincetti
Issue Date:March 2000
pp. 385
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design productivity is greatly enhanced. However, in the new design flow, validatio...
 
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts
Found in: On-Line Testing Symposium, IEEE International
By P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella, M. Sonza Reorda
Issue Date:July 2010
pp. 29-34
This paper reports and analyzes the results of alpha radiation testing campaigns on an embedded microprocessor manufactured with different standard cell libraries, each one enforcing Design for Manufacturing rules at a specific level. A set of analog simul...
 
Extended Fault Detection Techniques for Systems-on-Chip
Found in: Design and Diagnostics of Electronic Circuits and Systems
By P. Bernardi, L. Bolzani, M. Sonza Reorda
Issue Date:April 2007
pp. 1-6
The adoption of Systems-on-Chip (SoCs) in different types of applications represents an attracting solution. However, the high integration level of SoCs increases the sensitivity to transient faults and consequently introduces some reliability concerns. Se...
 
Automatic Generation of Validation Stimuli for Application-Specific Processors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By O. Goloubeva, M. Sonza Reorda, M. Violante
Issue Date:February 2004
pp. 10188
Microprocessor soft cores offer today an effective solution to the problem of rapidly developing new system-on-a-chips. However, all the features they offer are rarely used in embedded applications, and thus designers are often involved in the challenging ...
 
High-level test generation for hardware testing and software validation
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By O. Goloubeva, M. Sonza Reorda, M. Violante
Issue Date:November 2003
pp. 143-148
It is now common for design teams to develop systems where hardware and software components cooperate; they are thus facing the challenging task of validating and testing systems where hardware and software parts exist. In this paper a high-level test gene...
 
Comparing topological, symbolic and GA-based ATPGs: an experimental approach
Found in: Test Conference, International
By F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Issue Date:October 1996
pp. 39
The goal of this paper is to compare from an experimental point of view the performance of three ATPG tools for synchronous sequential circuits. The three tools are state-of-the-art implementations of the topological, symbolic, and GA-based approaches, res...
 
GARDA: a diagnostic ATPG for large synchronous sequential circuits
Found in: European Design and Test Conference
By F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Issue Date:March 1995
pp. 267
The paper deals with automated generation of diagnostic test sequences for synchronous sequential circuits. An algorithm is proposed, named GARDA, which is suitable to produce good results with acceptable CPU time and memory requirements even for the large...
 
FPGA-Based Fault Injection for Microprocessor Systems
Found in: Asian Test Symposium
By P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:November 2001
pp. 304
In this paper we propose an approach to speed-up Fault Injection campaigns for the evaluation of dependability properties of processor-based systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulat...
 
New Static Compaction Techniques of Test Sequences for Sequential Circuits
Found in: European Design and Test Conference
By F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Issue Date:March 1997
pp. 37
This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others elimi...
 
A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing
Found in: Asian Test Symposium
By P. Bernardi,M. Sonza Reorda
Issue Date:November 2011
pp. 142-147
This paper deals with the on-line test of SoCs including cores equipped with BIST circuitry and IEEE 1500 wrappers. A method is proposed, which exploits an Infrastructure IP named OTC to manage the on-line test, the OTC module activates the test and provid...
 
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Lagos-Benites,M. Grosso,M. Sonza Reorda,G. Audisio,M. Pipponzi,M. Sabatini,V.A. Avantaggiati
Issue Date:October 2011
pp. 391-398
Integrated transceivers play a leading role in an ever-increasing range of systems and applications where dependability is a major concern. In order to reduce time-to-market, it is crucial to verify the correctness of the hardware and software implementati...
 
Fault Injection-based Reliability Evaluation of SoPCs
Found in: European Test Symposium, IEEE
By M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
Issue Date:May 2006
pp. 75-82
Systems-on-Programmable-Chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming v...
 
19.2 On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
Found in: VLSI Test Symposium, IEEE
By F. Corno, N. Gaudenzi, P. Prinetto, M. Sonza Reorda
Issue Date:April 1998
pp. 424
No summary available.
 
A hardware accelerated framework for the generation of design validation programs for SMT processors
Found in: Design and Diagnostics of Electronic Circuits and Systems
By D. Ravotto, E. Sanchez, M. Sonza Reorda
Issue Date:April 2010
pp. 289-292
In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. The two major characteristics of the proposed framework are an effective method to gather information about the...
 
System Safety through Automatic High-Level Code Transformations: an Experimental Evaluation
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
Issue Date:March 2001
pp. 0297
Abstract: This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularl...
 
Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
Found in: VLSI Test Symposium, IEEE
By M. Rebaudengo, M. Sonza Reorda
Issue Date:April 1999
pp. 452
Fault Injection is a viable solution for verifying the correct design and implementation of Fault Tolerance mechanisms at different levels (hardware and software). The paper discusses the use of the Background Diagnostic Mode (BDM), available on several Mo...
 
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
Found in: European Test Symposium, IEEE
By D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
Issue Date:May 2009
pp. 93-98
Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and o...
 
Hybrid Soft Error Detection by Means of Infrastructure IP Cores
Found in: On-Line Testing Symposium, IEEE International
By L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
Issue Date:July 2004
pp. 79
High integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing adequate dependability levels more difficult then ever. In this paper we propose to adopt low-cost infrastructure-intellectual-...
 
Analysis of SEU Effects in a Pipelined Processor
Found in: On-Line Testing Workshop, IEEE International
By M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:July 2002
pp. 112
Modern processors embed features such as pipelined execution units and cache memories that can hardly be controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are no longer suitable for asse...
 
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures
Found in: On-Line Testing Workshop, IEEE International
By M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
Issue Date:July 2000
pp. 17
This paper deals with a method able to provide a mi-coprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations, which can automatically be applied, thus gre...
 
Dependability Analysis of CAN Networks: An Emulation-Based Approach
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Pérez, M. Sonza Reorda, M. Violante
Issue Date:November 2003
pp. 537
Today many safety-critical applications are based on distributed systems where several computing nodes exchange information via suitable network interconnections. An example of this class of applications is the automotive field, where developers are exploi...
 
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
Found in: On-Line Testing Symposium, IEEE International
By M. Sonza Reorda, M. Violante
Issue Date:July 2003
pp. 101
Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-relat...
 
Exploiting FPGA for Accelerating Fault Injection Experiments
Found in: On-Line Testing Workshop, IEEE International
By P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:July 2001
pp. 0009
Abstract: The widespread adoption of VLSI devices for safety-critical applications asks for effective tools for the evaluation and validation of their reliability. Fault Injection is commonly adopted for this task, and the effectiveness of the adopted tech...
 
Automatic Test Bench Generation for Simulation-based Validation
Found in: Hardware/Software Co-Design, International Workshop on
By M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:May 2000
pp. 136
In current design practice synthesis tools play a key role, letting designers to concentrate on the specification of the system being designed by carrying out repetitive tasks such as architecture synthesis and technology mapping. However, in the new desig...
 
System-Level Test Bench Generation in a Co-Design Framework
Found in: European Test Workshop, IEEE
By M. Lajolo, M. Rebaudengo, M. Sonza Reorda, M. Violante, L. Lavagno
Issue Date:May 2000
pp. 25
Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when System-on-Chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically gene...
 
A Genetic Algortithm for Automatic Generation of Test Logic for Digital Circuits
Found in: Tools with Artificial Intelligence, IEEE International Conference on
By F. Corno, P. Prinetto, M. Sonza Reorda
Issue Date:November 1996
pp. 10
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the...
 
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs
Found in: IEEE Transactions on Dependable and Secure Computing
By P. Bernardi, L.M. Bolzani Poehls, M. Grosso, M. Sonza Reorda
Issue Date:October 2010
pp. 439-445
Critical applications based on Systems-on-Chip (SoCs) require suitable techniques that are able to ensure a sufficient level of reliability. Several techniques have been proposed to improve fault detection and correction capabilities of faults affecting So...
 
Evaluating Alpha-induced soft errors in embedded microprocessors
Found in: On-Line Testing Symposium, IEEE International
By P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello
Issue Date:June 2009
pp. 69-74
This paper presents the results of Alpha Single Event Upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for differ...
 
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Found in: Microprocessor Test and Verification, International Workshop on
By P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
Issue Date:November 2005
pp. 55-62
Semiconductor manufacturers aim at delivering new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended ...
 
A New Functional Fault Model for FPGA Application-Oriented Testing
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Rebaudengo, M. Sonza Reorda, M. Violante
Issue Date:November 2002
pp. 372
The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates that the faults affecting the bit cells of the Look-Up Tables (LUTs) are not re...
 
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
Issue Date:February 2004
pp. 10584
This paper analyses the effects of Single Event Upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools d...
 
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
Found in: On-Line Testing Symposium, IEEE International
By W.J. Perez, J. Velasco, D. Ravotto, E. Sanchez, M. Sonza Reorda
Issue Date:July 2008
pp. 143-148
Software-Based Self-Test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requ...
 
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