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Displaying 1-19 out of 19 total
A general time domain approach for the design of perfect reconstruction modulated filter banks
Found in: Acoustics, Speech, and Signal Processing, IEEE International Conference on
By M. Poize, M. Renaudin, P. Venier
Issue Date:April 1993
pp. 221-224
A general temporal approach to the design of modulated filter banks is presented. A general framework has been developed which tackles the general problem of expanding a finite and discrete signal into a lapped, orthogonal or not, time-modulated set of fun...
 
Asynchronous Circuits Sensitivity to Fault Injection
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle
Issue Date:July 2004
pp. 121
This paper presents an analysis of the faults sensitivity of Quasi Delay Insensitive (QDI) asynchronous circuits. Faults considered in this work can be either natural or intentional. However, fault injection attacks which consist in causing an intentional ...
 
Asynchronous FIR Filters: Towards a New Digital Processing Chain
Found in: Asynchronous Circuits and Systems, International Symposium on
By F. Aeschlimann, E. Allier, L. Fesquet, M. Renaudin
Issue Date:April 2004
pp. 198-206
This paper is a contribution to the definition of a new kind of digital signal processing chain. It is focused on Finite-Impulse-Response filtering (FIR) applied to irregularly sampled signals obtained from an asynchronous analog to digital converter. The ...
 
A programmable logic architecture for prototyping clockless circuits
Found in: International Conference on Field Programmable Logic and Applications
By L. Fesquet, M. Renaudin
Issue Date:August 2005
pp. 293-298
This paper presents a novel programmable logic device (PLD) architecture for implementing and prototyping various styles of clockless or asynchronous circuits. Many classes of asynchronous circuits exist, depending on the timing assumptions that are made a...
 
A New Class of Asynchronous A/D Converters Based on Time Quantization
Found in: Asynchronous Circuits and Systems, International Symposium on
By E. Allier, G. Sicard, L. Fesquet, M. Renaudin
Issue Date:May 2003
pp. 196
This work is a contribution to a drastic change in standard signal processing chains. The main objective is to reduce the power consumption by one or two orders of magnitude. Integrated Smart Devices and Communicating Objects are application domains target...
 
Self timed division and square-root extraction
Found in: VLSI Design, International Conference on
By A. Guyot, M. Renaudin, B. El Hassan, V. Levering
Issue Date:January 1996
pp. 376
This paper describes a self-timed integrated circuit for division and square-root extraction. First it concentrates on the development and the proof of a new mathematical algorithm. Then the design methodology and the architecture of a self-timed circuit i...
 
Hardening Techniques against Transient Faults for Asynchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle
Issue Date:July 2005
pp. 129-134
This paper presents hardening techniques against transient faults for Quasi Delay Insensitive (QDI) circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. ...
 
High Security Smartcards
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. Renaudin, F. Bouesse, Ph. Proust, J. P. Tual, L. Sourgen, F. Germain
Issue Date:February 2004
pp. 10228
<p>New consumer appliances such as PDA, Set Top Box, GSM/UMTS terminals enable an easy access to the internet and strongly contribute to the development of e-commerce and m-commerce services. Tens of billion payments are made using cards today, and t...
 
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle, N. Feyt, P. Moitrel, F. M'Buwa Nzenguet
Issue Date:July 2006
pp. 125-130
This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying the countermeasures was previously published in IOLTS 2005. For the first time this work reports a practi...
 
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
Found in: Asynchronous Circuits and Systems, International Symposium on
By E. Beigné, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin
Issue Date:March 2005
pp. 54-63
The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new Asynchronous Network-On-Chip (NOC) architecture which provides low ...
 
Asynchronous SRT Dividers: The Real Cost
Found in: European Design and Test Conference
By H. Boutamine, A. Guyot, B. Elhassan, M. Renaudin
Issue Date:March 1996
pp. 195
No summary available.
 
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation
Found in: Asynchronous Circuits and Systems, International Symposium on
By D. Caucheteux, E. Beigne, E. Crochon, M. Renaudin
Issue Date:March 2006
pp. 86-97
This paper describes an original solution for improving inductive contactless telemetry powered devices. Rather than implementing asynchronous logic to provide digital circuit performance, we propose to apply the asynchronous logic paradigm to the whole sy...
 
FPGA Architecture for Multi-Style Asynchronous Logic
Found in: Design, Automation and Test in Europe Conference and Exhibition
By N. Huot, H. Dubreuil, L. Fesquet, M. Renaudin
Issue Date:March 2005
pp. 32-33
This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of ...
   
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle
Issue Date:July 2007
pp. 113-120
Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of Quasi Delay Insensitive (QDI) asynchronous circuits in the presence of SEUs (m...
 
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J. Rigaud, L. Fesquet, M. Renaudin, J. Quartana
Issue Date:March 2002
pp. 1090
No summary available.
   
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
Found in: Asynchronous Circuits and Systems, International Symposium on
By M. Renaudin, P. Vivet, F. Robin
Issue Date:April 1999
pp. 135
No summary available.
 
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor
Found in: Asynchronous Circuits and Systems, International Symposium on
By M. Renaudin, P. Vivet, F. Robin
Issue Date:April 1998
pp. 0022
The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execut...
 
Comparing transient-fault effects on synchronous and on asynchronous circuits
Found in: On-Line Testing Symposium, IEEE International
By R. Possamai Bastos, Y. Monnet, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis
Issue Date:June 2009
pp. 29-34
A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the pa...
 
Asynchronous circuits transient faults sensitivity evaluation
Found in: Proceedings of the 42nd annual conference on Design automation (DAC '05)
By M. Renaudin, R. Leveugle, Y. Monnet
Issue Date:June 2005
pp. 863-868
This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of...
     
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