Search For:

Displaying 1-16 out of 16 total
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs
Found in: On-Line Testing Symposium, IEEE International
By P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis
Issue Date:July 2006
pp. 235-241
In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We prop...
 
Software-Based Self-Test for Pipelined Processors: A Case Study
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By M. Hatzimihail, M. Psarakis, G. Xenoulis, D. Gizopoulos, A. Paschalis
Issue Date:October 2005
pp. 535-543
<p>Software-Based Self-Test (SBST) for processors and processor-based systems recently captured the interest of test technology researchers and practitioners due to its several advantages over traditional hardware Built-In Self-Test (BIST). In this p...
 
On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis
Issue Date:September 2007
pp. 379-397
On-line periodic testing of microprocessors is a viable low-cost alternative for a wide variety of embedded systems which cannot afford hardware or software redundancy techniques but necessitate the detection of intermittent or permanent faults. Low-cost, ...
 
Enhanced self-configurability and yield in multicore grids
Found in: On-Line Testing Symposium, IEEE International
By E. Kolonis, M. Nicolaidis, D. Gizopoulos, M. Psarakis, J.H. Collet, P. Zajac
Issue Date:June 2009
pp. 75-80
As we move deeper in the nanotechnology era, computer architecture is solicited to manipulate tremendous numbers of devices per chip with high defect densities. These trends provide new computing opportunities but efficiently exploiting them will require a...
 
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Apostolakis, D. Gizopoulos, M. Psarakis, A. Paschalis
Issue Date:March 2008
pp. 1304-1309
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first...
 
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Found in: Quality Electronic Design, International Symposium on
By N. Kranitis, M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian
Issue Date:March 2001
pp. 343
Effective Built-In Self-Test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regu...
 
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs
Found in: On-Line Testing Symposium, IEEE International
By A. Apostolakis, M. Psarakis, D. Gizopoulos, A. Paschalis
Issue Date:July 2007
pp. 271-276
Functional Software-Based Self-Testing (SBST) of mi-croprocessors and processor-based testing of Systems-on-Chip (SoCs) have recently attracted the attention of test technology research community because they provide an effective alternative to other tradi...
 
Deterministic Software-Based Self-Testing of Embedded Processor Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian
Issue Date:March 2001
pp. 0092
Abstract: A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage with...
 
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers
Found in: VLSI Test Symposium, IEEE
By M. Psarakis, A. Paschalis, N. Kranitis, D. Gizopoulos, Y. Zorian
Issue Date:April 2001
pp. 0015
The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been prop...
 
Architectures for online error detection and recovery in multicore processors
Found in: 2011 Design, Automation & Test in Europe
By D Gizopoulos,M Psarakis,S V Adve,P Ramachandran,S K S Hari,D Sorin,A Meixner,A Biswas,X Vera
Issue Date:March 2011
pp. 1-6
The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chip...
   
Effective Low Power BIST for Datapaths
Found in: Design, Automation and Test in Europe Conference and Exhibition
By D. Gizopoulos, N. Kranitis, M. Psarakis, A. Paschalis, Y. Zorian
Issue Date:March 2000
pp. 757
Power in processing cores (microprocessors, DSPs) is primarily consumed in the datapath part. Among the datapath functional modules, multipliers consume the largest amount of power due to their size and complexity. We propose a low power BIST scheme for da...
 
An Effective BIST Architecture for Fast Multiplier Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By A. Paschalis, N. Kranitis, M. Psarakis, D. Gizopoulos, Y. Zorian
Issue Date:March 1999
pp. 117
Wallace tree summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex Ics requ...
 
Low Power/Energy BIST Scheme for Datapaths
Found in: VLSI Test Symposium, IEEE
By D. Gizopoulos, N. Kranitis, M. Psarakis, A Paschalis, Y. Zorian
Issue Date:May 2000
pp. 23
Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for ...
 
Functional self-testing for bus-based symmetric multiprocessors
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By A. Apostolakis, A. Paschalis, D. Gizopoulos, M. Psarakis
Issue Date:March 2008
pp. 1-30
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first...
     
Effective low power BIST for datapaths (poster paper)
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '00)
By A. Paschalis, D. Gizopoulos, M. Psarakis, N. Kranitis, Y. Zorian
Issue Date:March 2000
pp. 757
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
An effective BIST architecture for fast multiplier cores
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '99)
By A. Paschalis, D. Gizopoulos, M. Psarakis, N. Kranitis, Y. Zorian
Issue Date:January 1999
pp. 28-es
In this paper, we consider the new and evocative work on tangible interfaces and the issues this raises in the light of some old lessons of HCI. In doing so, we make the point that many of these lessons of good design still apply, even when we are consider...
     
 1