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LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
Found in: IEEE Design & Test of Computers
By Y. Yamato,X. Wen,M. Kochte,K. Miyase,S. Kajihara,L. Wang
Issue Date:October 2012
pp. 1
Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing failure, which arises from excessive switching activity in t...
SAT-based fault coverage evaluation in the presence of unknown values
Found in: 2011 Design, Automation & Test in Europe
By M A Kochte,H-J Wunderlich
Issue Date:March 2011
pp. 1-6
Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time ...