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Displaying 1-9 out of 9 total
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements
Found in: IEEE Design and Test of Computers
By Muhammad Bashir, Linda Milor
Issue Date:September 2009
pp. 18-27
<p>Editor's note:</p><p>Low-<it>k</it> dielectric breakdown and stress migration have emerged as new sources of wearout for on-chip interconnect. This article analyzes statistical data from a 45-nm test chip and constructs a m...
A comparative study of wearout mechanisms in state-of-art microprocessors
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Chang-Chih Chen,Fahad Ahmed,Linda Milor
Issue Date:September 2012
pp. 271-276
In this work, we perform a comparative study of different wearout mechanisms affecting the state-of-art microprocessor systems. Taking into account the detailed thermal and electrical stress profiles, we present a methodology to accurately estimate the lif...
Fast Variation-Aware Statistical Dynamic Timing Analysis
Found in: Computer Science and Information Engineering, World Congress on
By Seyed-Abdollah Aftabjahani, Linda Milor
Issue Date:April 2009
pp. 488-492
A statistical dynamic timing analysis framework is presented to study the impact of catastrophic defects and process variation on the delay behavior of a digital circuit considering the effect of gate switching on delays. It uses object-oriented programmin...
Timing Analysis with Compact Variation-Aware Standard Cell Models
Found in: Computer Science and Information Engineering, World Congress on
By Seyed-Abdollah Aftabjahani, Linda Milor
Issue Date:April 2009
pp. 475-479
A compact variation-aware timing model for standard cells is developed. It incorporates variations in the input waveform and loading, process parameters, and the environment into the cell timing model. PCA is used to form a compact model of a set of wavefo...
A BIST Solution for The Test of I/O Speed
Found in: Test Conference, International
By Cheng Jia, Linda Milor
Issue Date:October 2003
pp. 1023
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 ?m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-...
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits
Found in: Computer-Aided Design, International Conference on
By Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
Issue Date:November 2000
pp. 62
Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18?m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variabili...
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells
Found in: 2014 IEEE 32nd VLSI Test Symposium (VTS)
By Woongrae Kim,Linda Milor
Issue Date:April 2014
pp. 1-6
In this paper we present a Built-In Self Test (BIST) methodology for diagnosis of backend time-dependent dielectric breakdown (BTDDB), via voiding due to electromigration (EM), and stress-induced voiding (SIV) in SRAM cells. Our built-in self test methodol...
Simulation of Logic/IDDQ Tests for Resistive Shorts in Logic Circuits by Using Simplicial Approximation
Found in: IDDQ Testing, IEEE International Workshop on
By Hung-Jen Lin, Linda Milor
Issue Date:November 1997
pp. 114
Logic circuits in the presence of resistive shorts often exhibit analog behavior which can be computationally expensive to simulate. This paper introduces a numerical method called simplicial approximation for its application to simulation of logic/IDDQ te...
Computing Parametric Yield Adaptively using Local Linear Models
Found in: Design Automation Conference
By Mien Li, Linda Milor
Issue Date:June 1996
pp. 831-836
A divide-and-conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could be highly nonlinear functions of a large numbers of stochastic process disturbances,...