Search For:

Displaying 1-2 out of 2 total
Computer Architecture With Associative Processor Replacing Last Level Cache and SIMD Accelerator
Found in: IEEE Transactions on Computers
By Leonid Yavits,Amir Morad,Ran Ginosar
Issue Date:November 2013
pp. 1
This study presents a computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor. Associative Processor combines data storage and data processing, and functions as a massively parallel SIMD processor and ...
 
Cache Hierarchy Optimization
Found in: IEEE Computer Architecture Letters
By Leonid Yavits,Amir Morad,Ran Ginosar
Issue Date:July 2013
pp. 1
Abstract— Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CM...
 
 1