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Displaying 1-37 out of 37 total
Arithmetic Operators Robust to Multiple Simultaneous Upsets
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By C. A. L. Lisbôa, L. Carro
Issue Date:October 2004
pp. 289-297
Future technologies, below 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. This way, together with process variability, design as known today is likely to change. Since many soft...
 
SET Fault Tolerant Combinational Circuits Based on Majority Logic
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Á. Michels, L. Petroli, C.A.L. Lisbôa, F. Kastensmidt, L. Carro
Issue Date:October 2006
pp. 345-352
This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. We propose a new type of voter circuit that uses some knowledge from the analog design arena, and show that these c...
 
Neutron radiation test of graphic processing units
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By P. Rech,C. Aguiar,R. Ferreira,C. Frost,L. Carro
Issue Date:June 2012
pp. 55-60
This paper reports and analyzes the results of neutrons radiation testing campaigns on a modern commercial-off-the-shelf Graphic Processing Unit (GPU). A set of guidelines for accelerated radiation experiments on CPUs is presented, emphasizing the shrewdne...
 
Matrix control-flow algorithm-based fault tolerance
Found in: On-Line Testing Symposium, IEEE International
By R. R. Ferreira,A. F. Moreira,L. Carro
Issue Date:July 2011
pp. 37-42
A novel software-implemented hardware fault tolerance method based on encoding both the control and the data-flow segments of programs with matrices is proposed and evaluated. Results show an average speed-up of 3 times compared to standard duplication and...
 
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs
Found in: 2011 Design, Automation & Test in Europe
By L Sterpone,L Carro,D Matos,S Wong,F Fakhar
Issue Date:March 2011
pp. 1-6
Power consumption is dramatically increasing for Static Random Access Memory Field Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new CAD tools are needed. Clock-gating methodologies have been applied in low power FPGA desi...
   
A fast error correction technique for matrix multiplication algorithms
Found in: On-Line Testing Symposium, IEEE International
By C. Argyrides, C. A. L. Lisboa, D. K. Pradhan, L. Carro
Issue Date:June 2009
pp. 133-137
Temporal redundancy techniques will no longer be able to cope with radiation induced soft errors in technologies beyond the 45 nm node, because transients will last longer than the cycle time of circuits. The use of spatial redundancy techniques will also ...
 
A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design
Found in: Engineering of Computer-Based Systems, IEEE International Conference on the
By L. Carro, A. Suzim
Issue Date:March 1996
pp. 382
This paper describes some modifications on the architecture of embedded Risc-like processors to better explore HW/SW parallelism in a HW/SW co-design environment. It is shown that the inclusion of an instruction memory allows parallel execution of the appl...
 
Impact of GPUs Parallelism Management on Safety-Critical and HPC Applications Reliability
Found in: 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
By P. Rech,L.L. Pilla,P.O.A. Navaux,L. Carro
Issue Date:June 2014
pp. 455-466
Graphics Processing Units (GPUs) offer high computational power but require high scheduling strain to manage parallel processes, which increases the GPU cross section. The results of extensive neutron radiation experiments performed on NVIDIA GPUs confirm ...
 
Online hardening of programs against SEUs and SETs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By C. A. L. Lisbôa, L. Carro, M. Sonza Reorda, M. Violante
Issue Date:October 2006
pp. 280-290
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (S...
 
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By F. Lima Kastensmidt, L. Sterpone, L. Carro, M. Sonza Reorda
Issue Date:March 2005
pp. 1290-1295
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing f...
 
The Impact of NoC Reuse on the Testing of Core-based Systems
Found in: VLSI Test Symposium, IEEE
By E. Cota, M. Kreutz, C.A. Zeferino, L. Carro, M. Lubaszewski, A. Susin
Issue Date:May 2003
pp. 128
The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to re...
 
Test Planning and Design Space Exploration in a Core-Based Environment
Found in: Design, Automation and Test in Europe Conference and Exhibition
By E. Cota, L. Carro, M. Lubaszewski, A. Orailoglu
Issue Date:March 2002
pp. 0478
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the consideration of different optimization factors (area, pins and test time) during the gl...
 
Designing a Radiation Hardened 8051-Like Micro-Controller
Found in: Integrated Circuit Design and System Design, Symposium on
By F.G. de Lima, E. Cota, L. Carro, M. Lubaszewski, R. Reis, R. Velazco, S. Rezgui
Issue Date:September 2000
pp. 255
This paper presents a prototype of a hardened version of the 8051 micro-controller, able to assure reliable operation in the presence of bit flips caused by radiation. Aiming at avoiding such faults in the 8051 micro-controller, Hamming code protection was...
 
Improving Logic Density of QCL Masterslices by using Universal Logic Gates
Found in: Integrated Circuit Design and System Design, Symposium on
By J. Güntzel, M. Johann, L. Carro, F. Gusmao de Lima, R. Reis
Issue Date:February 1998
pp. 204
No summary available.
 
Prototyping and reengineering of microcontroller-based systems
Found in: Rapid System Prototyping, IEEE International Workshop on
By L. Carro, A. Suzim
Issue Date:June 1996
pp. 178
This paper describes our current research in the field of systems design, trying to reach an Application Specific Integrated System (ASIS). Our target system is based on industry applications. We show the design approach to change presently developed board...
 
A Statistical Sampler for Increasing Analog Circuits Observability
Found in: Integrated Circuit Design and System Design, Symposium on
By M. Negreiros, L. Carro, A. A. Susin
Issue Date:September 2002
pp. 141
This paper presents a method to increase the observability of analog circuits through the use of a statistical sampler. This sampler acquires statistical properties of the input signal. Its main advantages are simplicity, low analog area overhead and suita...
 
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller
Found in: On-Line Testing Workshop, IEEE International
By F. Lima, L. Carro, R. Velazco, R. Reis
Issue Date:July 2002
pp. 194
This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming Code in the presence of multiple upsets. Upsets were randomly injected in all sensitive parts of the design. The experiment was e...
   
A Statistical Sampler for a New On-line Analog Test Method
Found in: On-Line Testing Workshop, IEEE International
By M. Negreiros, L. Carro, A. A. Susin
Issue Date:July 2002
pp. 79
In this work a new strategy to the on-line test of analog circuits is presented. The technique presents a very low analog overhead and it is completely digital. For the System-on-Chip (SoC) environment, this allows the implementation of on-line test using ...
 
TI-BIST: a temperature independent analog BIST for switched-capacitor filters
Found in: Asian Test Symposium
By L. Carro, E. Cota, M. Lubaszewski, Y. Bertrand, F. Azais, M. Renovell
Issue Date:December 2000
pp. 78
This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem o...
 
System Design using ASIPs
Found in: Engineering of Computer-Based Systems, IEEE International Conference on the
By L. Carro, G.A. Pereira, C. Alba, A. Suzim
Issue Date:March 1996
pp. 80
This paper describes our current research in the field of systems design, trying to reach an Application Specific System Integration (ASIS). We try to go beyond circuit integration to reach systems integration, using Application Specific Processors (ASIPs)...
 
Multiple Bit Error Detection and Correction in Memory
Found in: Digital Systems Design, Euromicro Symposium on
By J.F. Tarillo, N. Mavrogiannakis, C.A. Lisboa, C. Argyrides, L. Carro
Issue Date:September 2010
pp. 652-657
Technology evolution provides ever increasing density of transistors in chips, lower power consumption and higher performance. In this environment the occurrence of multiple-bit upsets (MBUs) becomes a significant concern. Critical applications need high r...
 
Reconfigurable communications for image processing applications
Found in: Parallel and Distributed Processing Symposium, International
By A.B. Soares,L. Carro,A.A. Susin
Issue Date:April 2006
pp. 223
This work tries to reuse programmable communication resources like a network-on-chip (NoC) in the acceleration of image applications. We show a mathematical model for the computation and communication pattern of two distributed motion estimation algorithms...
 
An Improved RF Loopback for Test Time Reduction
Found in: Design, Automation and Test in Europe Conference and Exhibition
By M. Negreiros, L. Carro, A.A. Susin
Issue Date:March 2006
pp. 141
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources in order to minimize the test overhead. An RF sampler is used to observe spect...
 
A Noise Generator for Analog-to-Digital Converter Testing
Found in: Integrated Circuit Design and System Design, Symposium on
By M. G. C. Flores, M. Negreiros, L. Carro, A. A. Susin
Issue Date:September 2002
pp. 135
This paper describes the implementation of a white noise generator to be used as the input signal of a new method for testing analog-to-digital converters in order to detect and to evaluate integral and differential non-linearity errors. The main goal of t...
 
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy
Found in: Integrated Circuit Design and System Design, Symposium on
By R. Hentschke, F. Marques, F. Lima, L. Carro, A. Susin, R. Reis
Issue Date:September 2002
pp. 95
This work compares two fault tolerance techniques, Hamming code and Triple Modular Redundancy (TMR), that are largely used to mitigate Single Event Upsets in integrated circuits, in terms of area and performance penalty. Both techniques were implemented in...
 
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
Found in: European Test Symposium, IEEE
By C.A. Lisboa, M.I. Erigson, L. Carro
Issue Date:May 2007
pp. 165-172
The evolution of the technology in search of smaller and faster devices brings along the need for a new paradigm in the design of circuits tolerant to soft errors. The current assumption of transient pulses shorter than the cycle time of the circuit will n...
 
Analysis and Implementation of a Stochastic Multiplier for Electrical Power Measurement
Found in: Integrated Circuit Design and System Design, Symposium on
By A. B. Soares, M. Negreiros, L. Carro, A. A. Susin
Issue Date:September 2002
pp. 9
In this work the analysis and implementation of an electrical power measurement device using stochastic arithmetic techniques is presented. The device was implemented using programmable logic and a 2-channel AD converter. Simulations and real measurements ...
 
FPGA Architecture Comparison for Non-Conventional Signal Processing
Found in: Neural Networks, IEEE - INNS - ENNS International Joint Conference on
By D. Franco, L. Carro
Issue Date:July 2000
pp. 2055
In the design of a specific application requiring scalar processing and a neural network, it was noticed that the same underlying hardware used to process analog signals could be used as another way to implement neural networks. This paper presents the mai...
 
F-Timer: Dedicated FPGA to Real-Time Systems Design Support
Found in: Real-Time Systems, Euromicro Conference on
By A. Parisoto, A. Souza, Jr., L. Carro, M. Pontremoli, C. Pereira, A. Suzim
Issue Date:June 1997
pp. 35
This paper presents a hardware architecture and its FPGA implementation for Real-Time operating systems support. Dedicated hardware units are responsible for the maintenance of a 32 tasks list organized by time priority. The co-processor also communicates ...
 
Experimental evaluation of thread distribution effects on multiple output errors in GPUs
Found in: 2013 18th IEEE European Test Symposium (ETS)
By P. Rech,C. Aguiar,C. Frost,L. Carro
Issue Date:May 2013
pp. 1-6
Graphic Processing Units are very prone to be corrupted by neutrons. Experimental results show that in the majority of the cases a typical application like matrix multiplication is affected by multiple output errors. In this paper we evaluate how different...
   
Neutron sensitivity of integer and floating point operations executed in GPUs
Found in: 2013 14th Latin American Test Workshop - LATW
By P. Rech,C. Aguiar,C. Frost,L. Carro
Issue Date:April 2013
pp. 1-6
Graphics Processing Units are very prone to be corrupted by neutrons. Experimental results obtained irradiating the GPU with high energy neutrons show that the input data type has a strong influence on the neutron-induced error rate of the executed algorit...
   
Reconfiguration of embedded Java applications
Found in: Parallel and Distributed Processing Symposium, International
By J.C.S. Otero,F.R. Wagner,L. Carro
Issue Date:April 2006
pp. 215
This work presents the development of a coarse grain reconfigurable unit to be coupled to a native Java microcontroller, which is designed for an optimized execution of the embedded application. Code fragments to be accelerated through this unit are identi...
 
Increasing analog programmability in SoCs
Found in: Parallel and Distributed Processing Symposium, International
By E. Schuler,L. Carro
Issue Date:April 2006
pp. 208
The use of programmability in systems-on-chip (SoC) brings as the main advantage the possibility of reducing the time-to-market and the cost of design, specially when different systems and functions must cover different markets, going from low-power and lo...
 
A Comparison of Microcontrollers Targeted to FPGA-Based Embedded Applications
Found in: Integrated Circuit Design and System Design, Symposium on
By S.A. Ito, L. Carro
Issue Date:September 2000
pp. 397
There is available today a large amount of microcontroller cores to the embedded market, ranging from classical architectures like the 8051 to RISC or DSP machines. The choice among different architectures depends of parameters like speed, power installed ...
 
Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels
Found in: Integrated Circuit Design and System Design, Symposium on
By E.A.C. da Costa, F.P. Cortes, R. Cardoso, L. Carro, S. Bampi
Issue Date:September 2000
pp. 222
This paper proposes an analytical modeling of power consumption in CMOS gates which is based on timing-only models. The proposed model is refined for the short circuit power dissipation as a function of input transition times, power supply voltage and outp...
 
A Comparison of OO and Reactive Based Specifications on the Design of Embedded Systems
Found in: Integrated Circuit Design and System Design, Symposium on
By S.A. Ito, J.C.B. de Mattos, L. Carro, S.S. Toscani
Issue Date:September 2000
pp. 391
The growing complexity of embedded systems has claimed more abstract approaches in order to apply some kind of system-level design methodology. Java is a natural candidate for system design language, due to its well known software compatibility and object-...
 
Reliability aware yield improvement technique for nanotechnology based circuits
Found in: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes (SBCCI '09)
By C. A. Lisboa, C. Argyrides, D. K. Pradhan, G. Dimosthenous, L. Carro
Issue Date:August 2009
pp. 1-6
Lithography based IC manufacturing is approaching its physical limits in terms of feature size. In this scenario, nanotechnology based manufacturing, relying on self-assembly of nanotubes or nanowires, has been predicted as an alternative to CMOS technolog...
     
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