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Displaying 1-32 out of 32 total
Reducing the Communication of Message-Passing Systems Synthesized from Synchronous Programs
Found in: 2014 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
By Daniel Baudisch, Yu Bai,Klaus Schneider
Issue Date:February 2014
pp. 444-451
This paper presents a method to translate a given synchronous system to a multithreaded system where process nodes communicate via channels with each other. It is well-known that the reduction of communication has been identified to be a crucial key for ef...
 
Automatic Hard Block Inference on FPGAs
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By Adrian Willenbucher,Klaus Schneider
Issue Date:September 2013
pp. 551-557
Modern FPGAs often provide a number of highly optimized hard IP blocks with certain functionalities. However, manually instantiating these blocks is both time-consuming and error-prone, in particular, if only a part of the functionality of the IP block is ...
 
Embedding Polychrony into Synchrony
Found in: IEEE Transactions on Software Engineering
By Jens Brandt,Mike Gemunde,Klaus Schneider,Sandeep K. Shukla,Jean-Pierre Talpin
Issue Date:July 2013
pp. 917-929
This paper presents an embedding of polychronous programs into synchronous ones. Due to this embedding, it is not only possible to deepen the understanding of these different models of computation, but, more importantly, it is possible to transfer compilat...
 
Location-Aware Traffic Analysis of a Peer-to-Peer Streaming Application in a HSPA Network
Found in: 2013 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
By Philipp M. Eittenberger,Klaus Schneider,Udo R. Krieger
Issue Date:February 2013
pp. 444-448
The amount of mobile video streaming traffic is rapidly growing and a potential candidate to reduce the load on the content delivery infrastructure is given by the peer-to-peer (P2P) paradigm. One might argue about the adequacy of P2P in this mobile contex...
 
Efficient Handling of Arrays in Dataflow Process Networks
Found in: 2012 IEEE 14th Int'l Conf. on High Performance Computing and Communication (HPCC) & 2012 IEEE 9th Int'l Conf. on Embedded Software and Systems (ICESS)
By Daniel Baudisch,Jens Brandt,Klaus Schneider
Issue Date:June 2012
pp. 1395-1402
Dataflow process networks (DPN) have been proposed as a programming model for distributed parallel systems that have communication paths with unpredictable latencies. The purely data-driven execution of DPNs does not require a global coordination and there...
 
Causality analysis of synchronous programs with refined clocks
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Mike Gemunde,Jens Brandt,Klaus Schneider
Issue Date:November 2011
pp. 25-32
Synchronous languages are based on the synchronous abstraction of time, which divides the execution of programs into an infinite sequence of macro steps that consist of finitely many micro steps. A well-studied problem of this model of computation are cycl...
 
Translating Synchronous Systems to Data-Flow Process Networks
Found in: Parallel and Distributed Computing Applications and Technologies, International Conference on
By Daniel Baudisch,Jens Brandt,Klaus Schneider
Issue Date:October 2011
pp. 354-361
The synchronous model of computation (MoC) has been successfully used for the design of embedded systems having a local control like hardware circuits and single-threaded software, while its application to distributed parallel embedded systems is still a c...
 
Data-Flow Analysis of Extended Finite State Machines
Found in: Application of Concurrency to System Design, International Conference on
By Yu Bai, Jens Brandt, Klaus Schneider
Issue Date:June 2011
pp. 163-172
In this paper, we present a static data-flow analysis for synchronous programs, which is used to improve the run-time efficiency of the generated code. Our optimization techniques are based on extended finite state machines (EFSMs) which are obtained by a ...
 
Predicting Events for the Simulation of Hybrid Systems
Found in: Computer and Information Technology, International Conference on
By Kerstin Bauer, Klaus Schneider
Issue Date:July 2010
pp. 1833-1840
The quality of the numeric simulation of hybrid systems highly depends on the capability of the simulator to detect discrete events during continuous evolutions. Due to the interaction of discrete and continuous dynamics, failures to detect such events may...
 
Desynchronizing Synchronous Programs by Modes
Found in: Application of Concurrency to System Design, International Conference on
By Jens Brandt, Mike Gemünde, Klaus Schneider
Issue Date:July 2009
pp. 32-41
The synchronous programming paradigm simplifies the specification and verification of reactive systems. However, synchronous programs must be often implemented on architectures that do not follow this model of computation (like distributed systems or syste...
 
A Formal Semantics of Clock Refinement in Imperative Synchronous Languages
Found in: Application of Concurrency to System Design, International Conference on
By Mike Gemünde, Jens Brandt, Klaus Schneider
Issue Date:June 2010
pp. 157-168
The synchronous model of computation divides the execution of a program into an infinite sequence of so-called macro steps, which are further divided into finitely many micro steps. Since all threads of a program are forced to run in lockstep, programmers ...
 
The Model Checking View to Clock Gating and Operand Isolation
Found in: Application of Concurrency to System Design, International Conference on
By Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep K. Shukla
Issue Date:June 2010
pp. 181-190
Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step procedure: first, they statically analyze a hardware circuit to determine irrelevant com...
 
Maximal Causality Analysis
Found in: Application of Concurrency to System Design, International Conference on
By Klaus Schneider, Jens Brandt, Tobias Schuele, Thomas Tuerk
Issue Date:June 2005
pp. 106-115
Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algorithms to analyze the consistency of such cycles usually extend data types by...
 
Global vs. Local Model Checking: A Comparison of Verification Techniques for Infinite State Systems
Found in: Software Engineering and Formal Methods, IEEE International Conference on
By Tobias Schuele, Klaus Schneider
Issue Date:September 2004
pp. 67-76
Global and local model checking procedures follow radically different paradigms: while global approaches are based on fixpoint computation, local approaches are related to deduction and induction. For the verification of finite state systems, this may resu...
 
Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis
Found in: Design Automation Conference
By Tobias Schuele, Klaus Schneider
Issue Date:June 2004
pp. 107-112
Various techniques have been proposed to determine the worst case execution time of real-time systems. For most of these approaches, it is not necessary to capture the complete semantics of the system. Instead, it suffices to analyze an abstract model prov...
 
Exact Runtime Analysis Using Automata-Based Symbolic Simulation
Found in: Formal Methods and Models for Co-Design, ACM/IEEE International Conference on
By Tobias Schüle, Klaus Schneider
Issue Date:June 2003
pp. 153
cIn this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into account the target architecture to obtain accurate estimates. The key idea i...
 
A Generalised Approach to Supervisor Synthesis
Found in: Formal Methods and Models for Co-Design, ACM/IEEE International Conference on
By Roberto Ziller, Klaus Schneider
Issue Date:June 2003
pp. 217
We present a generalisation of the supervisory control problem proposed by Ramadge and Wonham. The objective of that problem is to synthesise a controller which constrains a system's behaviour according to a given specification, ensuring controllability an...
 
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
Found in: Design, Automation and Test in Europe Conference and Exhibition
By G. Logothetis, Klaus Schneider
Issue Date:March 2003
pp. 10196
<p>In this paper, a novel approach to high-level (i.e. architecture independent) worst case execution time (WCET) analysis is presented that automatically computes exact bounds for all inputs. To this end, we make use of the distinction between micro...
 
The BDD Space Complexity of Different Forms of Concurrency
Found in: Application of Concurrency to System Design, International Conference on
By Michael Baldamus, Klaus Schneider
Issue Date:June 2001
pp. 231
Symbolic representations using binary decision diagrams (BDDs) are popular means to cope with extremely large state spaces. However, it may be the case that the BDD representation itself is prohibitively large. We consider the BDD representations of synchr...
 
Formal Specification in VHDL for Hardware Verification
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ralf Reetz, Klaus Schneider, Thomas Kropf
Issue Date:February 1998
pp. 257
In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statem...
 
Automatic Hard Block Inference on FPGAs
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By Adrian Willenbucher,Klaus Schneider
Issue Date:September 2013
pp. 551-557
Modern FPGAs often provide a number of highly optimized hard IP blocks with certain functionalities. However, manually instantiating these blocks is both time-consuming and error-prone, in particular, if only a part of the functionality of the IP block is ...
 
Targeting different abstraction layers by model-based design methods for embedded systems: A case study
Found in: 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
By Omair Rafique,Manuel Gesell,Klaus Schneider
Issue Date:August 2013
pp. 334-337
In this paper, we show how code can be generated at different levels of abstraction from a single source description. To this end, we use a model-driven development tool called Averest that is based on a synchronous programming language. We illustrate our ...
   
Monitoring distributed reactive systems
Found in: 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
By Yu Bai,Jens Brandt,Klaus Schneider
Issue Date:November 2012
pp. 84-91
Recent results on the desynchronization of synchronous systems introduced the subclass of so-called en-do/isochronous systems. Since the modules of these systems can derive their own local clocks from their inputs, they can be implemented as asynchronous c...
   
Welcome to ICCD 2011!
Found in: Computer Design, International Conference on
By Georgi Gaydadjiev,Sofiene Tahar,Greg Byrd,Klaus Schneider
Issue Date:October 2011
pp. IX-XIX
On behalf of the organizing and program committee, we would like to welcome you to the 29
   
Passive code in synchronous programs
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Jens Brandt, Klaus Schneider, Yu Bai
Issue Date:January 2014
pp. 1-25
The synchronous model of computation requires that in every step, inputs are read and outputs are synchronously computed as the reaction of the program. In addition, all internal variables are updated in parallel even though not all of these values might b...
     
A hoare calculus for the verification of synchronous languages
Found in: Proceedings of the sixth workshop on Programming languages meets program verification (PLPV '12)
By Klaus Schneider, Manuel Gesell
Issue Date:January 2012
pp. 37-48
The synchronous model of computation divides the execution of a program into macro steps that consist of finitely many atomic micro steps (like assignments). The micro steps of a macro step are executed within the same variable environment (i.e. in paralle...
     
From synchronous programs to symbolic representations of hybrid systems
Found in: Proceedings of the 13th ACM international conference on Hybrid systems: computation and control (HSCC '10)
By Kerstin Bauer, Klaus Schneider
Issue Date:April 2010
pp. 41-50
In this paper, we present an extension of the synchronous language Quartz by new kinds of variables, actions and statements for modeling the interaction of synchronous systems with their continuous environment. We present an operational semantics of the ob...
     
Translating concurrent action oriented specifications to synchronous guarded actions
Found in: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems (LCTES '10)
By Jens Brandt, Klaus Schneider, Sandeep K. Shukla
Issue Date:April 2010
pp. 4.6-4.16
Concurrent Action-Oriented Specifications (CAOS) model the be- havior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL). Previous approaches always considered the compila...
     
Separate compilation for synchronous programs
Found in: Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems (SCOPES '09)
By Jens Brandt, Klaus Schneider
Issue Date:April 2009
pp. 1-10
Esterel and other imperative synchronous languages offer a rich set of statements, which can be used to conveniently describe complex control behaviors in a concise, but yet precise way. In particular, the ability to arbitrarily nest all kinds of statement...
     
Three-valued automated reasoning on analog properties
Found in: Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI '07)
By Alexander Dreyer, Klaus Schneider, Raffaella Gentilini
Issue Date:March 2007
pp. 485-488
We deal with the problem of designing suitable languages for the modeling and the automatic verification of properties over analog circuits. To this purpose, we suitably enrich classical temporal logics with basic formul\ae allowing to model arbitrary func...
     
Verifying the adaptation behavior of embedded systems
Found in: Proceedings of the 2006 international workshop on Self-adaptation and self-managing systems (SEAMS '06)
By Klaus Schneider, Mario Trapp, Tobias Schuele
Issue Date:May 2006
pp. 16-22
Many complex embedded systems dynamically adapt their components, services, algorithms, and parameters to the environment. This leads to new classes of design errors, since adaptation has become an increasingly complex part of the systems' behavior. In par...
     
Combining supervisor synthesis and model checking
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Klaus Schneider, Roberto Ziller
Issue Date:May 2005
pp. 331-362
Model checking and supervisor synthesis have been successful in solving different design problems related to discrete systems in the last decades. In this paper, we analyze some advantages and drawbacks of these approaches and combine them for mutual impro...
     
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