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Displaying 1-27 out of 27 total
Virtual Execution Environments: Support and Tools
Found in: Parallel and Distributed Processing Symposium, International
By Apala Guha, Jason D. Hiser, Naveen Kumar, Jing Yang, Min Zhao, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Kim Hazelwood, Mary Lou Soffa
Issue Date:March 2007
pp. 299
In today's dynamic computing environments, the available resources and even underlying computation engine can change during the execution of a program. Additionally, current trends in software development favor the flexibility and cost-effectiveness of dyn...
 
Eliminating voltage emergencies via software-guided code transformations
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Gu-Yeon Wei, Gu-Yeon Wei, Kim Hazelwood, Kim Hazelwood, Meeta S. Gupta, Meeta S. Gupta, Michael D. Smith, Michael D. Smith, Simone Campanoni, Simone Campanoni, Vijay Janapa Reddi, Vijay Janapa Reddi
Issue Date:September 2010
pp. 1-28
In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These flu...
     
Where is the data? Why you cannot debate CPU vs. GPU performance without the answer
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Chris Gregg, Kim Hazelwood
Issue Date:April 2011
pp. 134-144
General purpose GPU Computing (GPGPU) has taken off in the past few years, with great promises for increased desktop processing power due to the large number of fast computing cores on high-end graphics cards. Many publications have demonstrated phenomenal...
 
Analyzing Parallel Programs with Pin
Found in: Computer
By Moshe (Maury) Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal
Issue Date:March 2010
pp. 34-41
No summary available.
 
Adaptive Online Context-Sensitive Inlining
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Kim Hazelwood, David Grove
Issue Date:March 2003
pp. 253
As current trends in software development move toward more complex object-oriented programming, inlining has become a vital optimization that provides substantial performance improvements to C++ and Java programs. Yet, the aggressiveness of the inlining al...
 
Code Cache Management Schemes for Dynamic Optimizers
Found in: Interaction between Compilers and Computer Architecture, Annual Workshop on
By Kim Hazelwood, Michael D. Smith
Issue Date:February 2002
pp. 102
A dynamic optimizer is a software-based system that performs code modifications at runtime, and several such systems have been proposed over the past several years. These systems typically perform optimization on the level of an instruction trace, and most...
 
Finding cool code: An analysis of source-level causes of temperature effects
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Dan Upton, Kim Hazelwood
Issue Date:April 2011
pp. 117-118
Temperature issues have become a first-order concern for microprocessors over the last several microprocessor generations. An increase in on-chip transistor density has led to increased power density and therefore higher on-die temperatures. Higher process...
 
Performance characterization of mobile-class nodes: Why fewer bits is better
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Michelle McDaniel, Kim Hazelwood
Issue Date:April 2011
pp. 131-132
Mobile-class nodes, also known as netbooks, have become increasingly popular in the personal computing market. As is the trend in the computing market, the processors in these mobile-class nodes moving from 32 bits to 64 bits. This move extends the memory ...
 
Design of a custom VEE core in a chip multiprocessor
Found in: Application Specific Processors, Symposium on
By Dan Upton, Kim Hazelwood
Issue Date:June 2010
pp. 97-100
Chip multiprocessors provide an opportunity for continuing performance growth in the face of limited single-thread parallelism. Although the best design path for such chips remains open, application-specific core designs have shown promise. This work consi...
 
SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Steven Wallace, Kim Hazelwood
Issue Date:March 2007
pp. 209-220
Dynamic instrumentation systems have proven to be extremely valuable for program introspection, architectural simulation, and bug detection. Yet a major drawback of modern instrumentation systems is that the instrumented applications often execute several ...
 
A Cross-Architectural Interface for Code Cache Manipulation
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Kim Hazelwood, Robert Cohn
Issue Date:March 2006
pp. 17-27
<p>Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of every instruction that executes, run-time access to a code cache can be ...
 
Improving Region Selection in Dynamic Optimization Systems
Found in: Microarchitecture, IEEE/ACM International Symposium on
By David Hiniker, Kim Hazelwood, Michael D. Smith
Issue Date:November 2005
pp. 141-154
<p>The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interprocedural path, or trace, as the unit of code optimization and code ...
 
Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization
Found in: Low Power Electronics and Design, International Symposium on
By Kim Hazelwood, David Brooks
Issue Date:August 2004
pp. 326-331
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations that stress the power-delivery network. Recent research has focused on hardware-o...
 
Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Kim Hazelwood, James E. Smith
Issue Date:March 2004
pp. 89
Dynamic optimization systems store optimized or translated code in a software-managed code cache in order to maximize reuse of transformed code. Code caches store superblocks that are not fixed in size, may contain links to other superblocks, and carry a h...
 
Generational Cache Management of Code Traces in Dynamic Optimization Systems
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Kim Hazelwood, Michael D. Smith
Issue Date:December 2003
pp. 169
A dynamic optimizer is a runtime software system that groups a program's instruction sequences into traces, optimizes those traces, stores the optimized traces in a software-based code cache, and then executes the optimized code in the code cache. To maxim...
 
Memory optimization of dynamic binary translators for embedded systems
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Apala Guha, Kim Hazelwood, Mary Lou Soffa
Issue Date:September 2012
pp. 1-29
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. DBT-based services are valuable for all types of platforms. However, the high memory demands of DBTs present an obstacle for embedded systems. Mos...
     
Runtime adaptation: a case for reactive code alignment
Found in: Proceedings of the 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (EXADAPT '12)
By Kim Hazelwood, Michelle McDaniel
Issue Date:March 2012
pp. 1-11
Static alignment techniques are well studied and have been incorporated into compilers in order to optimize code locality for the instruction fetch unit in modern processors. However, current static alignment techniques have several limitations that cannot...
     
EcoSim: a language and experience teaching parallel programming in elementary school
Found in: Proceedings of the 43rd ACM technical symposium on Computer Science Education (SIGCSE '12)
By Chris Gregg, James Cohoon, Luther Tychonievich, Kim Hazelwood
Issue Date:February 2012
pp. 51-56
Traditional introductory programming classes teach sequential programming using a single-threaded programming model. It is typical to wait until a student has developed proficiency in sequential programming before teaching parallel programming. As computer...
     
Analyzing program flow within a many-kernel OpenCL application
Found in: Proceedings of the Fourth Workshop on General Purpose Processing on Graphics Processing Units (GPGPU-4)
By Chris Gregg, David Kaeli, Kim Hazelwood, Norman Rubin, Perhaad Mistry
Issue Date:March 2011
pp. 1-8
Many developers have begun to realize that heterogeneous multi-core and many-core computer systems can provide significant performance opportunities to a range of applications. Typical applications possess multiple components that can be parallelized; deve...
     
Balancing memory and performance through selective flushing of software code caches
Found in: Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems (CASES '10)
By Apala Guha, Kim Hazelwood, Mary Soffa
Issue Date:October 2010
pp. 1-10
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all platforms, and especially embedded systems. The memory demand is typically co...
     
Scalable support for multithreaded applications on dynamic binary instrumentation systems
Found in: Proceedings of the 2009 international symposium on Memory management (ISMM '09)
By Greg Lueck, Kim Hazelwood, Robert Cohn
Issue Date:June 2009
pp. 70-73
Dynamic binary instrumentation systems are used to inject or modify arbitrary instructions in existing binary applications; several such systems have been developed over the past decade. Much of the literature describing the internal architecture and perfo...
     
Trace fragment selection within method-based JVMs
Found in: Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on Virtual execution environments (VEE '08)
By Duane Merrill, Kim Hazelwood
Issue Date:March 2008
pp. 1-1
Java virtual machines have historically employed either a "wholemethod" or a "trace" methodology for selecting regions of code for optimization. Adaptive whole-method optimization primarily leverages intra-procedural optimizations derived from classic stat...
     
A dynamic binary instrumentation engine for the ARM architecture
Found in: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems (CASES '06)
By Artur Klauser, Kim Hazelwood
Issue Date:October 2006
pp. 261-270
Dynamic binary instrumentation (DBI) is a powerful technique for analyzing the runtime behavior of software. While numerous DBI frameworks have been developed for general-purpose architectures, work on DBI frameworks for embedded architectures has been fai...
     
Managing bounded code caches in dynamic binary optimization systems
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By Kim Hazelwood, Michael D. Smith
Issue Date:September 2006
pp. 263-294
Dynamic binary optimizers store altered copies of original program instructions in software-managed code caches in order to maximize reuse of transformed code. Code caches store code blocks that may vary in size, reference other code blocks, and carry a hi...
     
Pin: building customized program analysis tools with dynamic instrumentation
Found in: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation (PLDI '05)
By Artur Klauser, Chi-Keung Luk, Geoff Lowney, Harish Patil, Kim Hazelwood, Robert Cohn, Robert Muth, Steven Wallace, Vijay Janapa Reddi
Issue Date:June 2005
pp. 280-280
Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we have developed a new instrumentation system called Pin. Our goals are to provide...
     
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Found in: Proceedings of the 2004 international symposium on Low power electronics and design (ISLPED '04)
By David Brooks, Kim Hazelwood
Issue Date:August 2004
pp. 326-331
Microprocessor designers use techniques such as clock gating toreduce power dissipation. An unfortunate side-effect of thesetechniques is the processor current fluctuations that stress thepower-delivery network. Recent research has focused onhardware-only ...
     
DBT path selection for holistic memory efficiency and performance
Found in: Proceedings of the 6th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments (VEE '10)
By Apala Guha, Kim hazelwood, Mary Lou Soffa
Issue Date:March 2010
pp. 145-156
Dynamic binary translators(DBTs) provide powerful platforms for building dynamic program monitoring and adaptation tools. DBTs, however, have high memory demands because they cache translated code and auxiliary code to a software code cache and must also m...
     
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