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Displaying 1-50 out of 76 total
Scalable Parallel Programming with CUDA
Found in: Queue
By Ian Buck, John Nickolls, John Nickolls, John Nickolls, John Nickolls, Kevin Skadron, Kevin Skadron, Kevin Skadron, Kevin Skadron, Michael Garland, Michael Garland, Michael Garland, Michael Garland
Issue Date:March 2008
pp. 40-53
The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems. Furthermore, their parallelism continues to scale with Moore's law. The challenge is to develop mainstream application software that transparentl...
     
Introducing the New Editor-in-Chief of the IEEE Computer Architecture Letters
Found in: IEEE Computer Architecture Letters
By Kevin Skadron
Issue Date:January 2013
pp. 1
The out-going Editor-in-Chief introduces Jose F. Martínez as the new Editor-in-Chief (EIC) of the IEEE Computer Architecture Letters (CAL). A brief professional biography is included. In addition, it is noted that CAL aims to provide fast-turnaround for ea...
 
Accelerating Compute-Intensive Applications with GPUs and FPGAs
Found in: Application Specific Processors, Symposium on
By Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadron, John Lach
Issue Date:June 2008
pp. 101-107
Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs, which can often achieve better performance than CPUs on certain ...
 
Low-Power Design and Temperature Management
Found in: IEEE Micro
By Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou
Issue Date:November 2007
pp. 46-57
One of the primary concerns for microprocessor designers has always been balancing power and thermal management while minimizing performance loss. Rather than generate solutions to this dilemma, the advent of multicore chips has raised a host of new challe...
 
Temperature-Aware Computer Systems: Opportunities and Challenges
Found in: IEEE Micro
By Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan
Issue Date:November 2003
pp. 52-61
<p>Temperature-aware design techniques have an important role to play in addition to traditional techniques like power-aware design and package- and board-level thermal engineering. These authors define the role of architecture techniques and describ...
 
Implications of the Power Wall: Dim Cores and Reconfigurable Logic
Found in: IEEE Micro
By Liang Wang,Kevin Skadron
Issue Date:September 2013
pp. 40-48
Near-threshold operation can increase the number of simultaneously active cores at the expense of much lower operating frequency ("dim silicon"), but dim cores suffer from diminishing returns as the number of cores increases. At this point, hardw...
 
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core
Found in: IEEE Micro
By Lukasz G. Szafaryn,Brett H. Meyer,Kevin Skadron
Issue Date:July 2013
pp. 56-65
As circuit feature sizes shrink, multibit errors become more significant, while previously unprotected combinational logic becomes more vulnerable, requiring a reevaluation of the resiliency design space within a processor core. The authors present Svalinn...
 
Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth
Found in: 2012 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)
By Jiayuan Meng,Jeremy W. Sheaffer,Kevin Skadron
Issue Date:May 2012
pp. 107-118
Architectures that aggressively exploit SIMD often have many data paths execute in lockstep and use multi-threading to hide latency. They can yield high through-put in terms of area- and energy-efficiency for many data-parallel applications. To balance pro...
 
Increasing Utilization in Modern Warehouse-Scale Computers Using Bubble-Up
Found in: IEEE Micro
By Jason Mars,Lingjia Tang,Kevin Skadron,Mary Lou Soffa,Robert Hundt
Issue Date:May 2012
pp. 88-99
Precisely predicting performance degradation due to colocating multiple executing applications on a single machine is critical for improving utilization in modern warehouse-scale computers (WSCs). Bubble-Up is the first mechanism for such precise predictio...
 
Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads
Found in: IEEE Workload Characterization Symposium
By Wim Heirman,Trevor E. Carlson,Shuai Che,Kevin Skadron,Lieven Eeckhout
Issue Date:November 2011
pp. 38-49
This paper proposes a methodology for analyzing parallel performance by building cycle stacks. A cycle stack quantifies where the cycles have gone, and provides hints towards optimization opportunities. We make the case that this is particularly interestin...
 
Dymaxion: optimizing memory access patterns for heterogeneous systems
Found in: SC Conference
By Shuai Che,Jeremy W. Sheaffer,Kevin Skadron
Issue Date:November 2011
pp. 1-11
Graphics processors (GPUs) have emerged as an important platform for general purpose computing. GPUs offer a large number of parallel cores and have access to high memory bandwidth; however, data structure layouts in GPU memory often lead to suboptimal per...
 
Editorial: Letter from the Editor-in-Chief
Found in: IEEE Computer Architecture Letters
By Kevin Skadron
Issue Date:January 2011
pp. 1-3
No summary available.
   
Temperature-Aware Architecture: Lessons and Opportunities
Found in: IEEE Micro
By Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, Kevin Skadron, Edmund Cheng
Issue Date:May 2011
pp. 82-86
<p>Managing temperature is an important concern in modern processor and other microelectronic chips. This column explores recent lessons and future challenges in temperature-aware design.</p>
 
Scaling with Design Constraints: Predicting the Future of Big Chips
Found in: IEEE Micro
By Wei Huang,Karthick Rajamani,Mircea R. Stan,Kevin Skadron
Issue Date:July 2011
pp. 16-29
The past few years have witnessed high-end processors with increasing numbers of cores and larger dies. With limited instruction-level parallelism, chip power constraints, and technology-scaling limitations, designers have embraced multiple cores rather th...
 
A reconfigurable simulator for large-scale heterogeneous multicore architectures
Found in: Performance Analysis of Systems and Software, IEEE International Symmposium on
By Jiayuan Meng, Kevin Skadron
Issue Date:April 2011
pp. 119-120
Future general purpose architectures will scale to hundreds of cores. In order to accommodate both latency-oriented and throughput-oriented workloads, the system is likely to present a heterogenous mix of cores. In particular, sequential code can achieve p...
 
Editorial: Letter from the Editor-in-Chief
Found in: IEEE Computer Architecture Letters
By Kevin Skadron
Issue Date:July 2010
pp. 37-44
No summary available.
   
Increasing memory miss tolerance for SIMD cores
Found in: SC Conference
By David Tarjan, Jiayuan Meng, Kevin Skadron
Issue Date:November 2009
pp. 1-11
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called
 
Predictive Temperature-Aware DVFS
Found in: IEEE Transactions on Computers
By Jong Sung Lee, Kevin Skadron, Sung Woo Chung
Issue Date:January 2010
pp. 127-133
In this paper, we propose predictive temperature-aware Dynamic Voltage and Frequency Scaling (DVFS) using the performance counters that are already embedded in commercial microprocessors. By using the performance counters and simple regression analysis, we...
 
Accelerating leukocyte tracking using CUDA: A case study in leveraging manycore coprocessors
Found in: Parallel and Distributed Processing Symposium, International
By Michael Boyer,David Tarjan,Scott T. Acton,Kevin Skadron
Issue Date:May 2009
pp. 1-12
The availability of easily programmable manycore CPUs and GPUs has motivated investigations into how to best exploit their tremendous computational power for scientific computing. Here we demonstrate how a systems biology application—detection and tracking...
 
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Found in: IEEE Transactions on Computers
By Wei Huang, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, Mircea R. Stan
Issue Date:September 2008
pp. 1277-1288
Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To achieve this, an accurate yet fast temperature model together...
 
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
Found in: IEEE Transactions on Computers
By Sung Woo Chung, Kevin Skadron
Issue Date:January 2008
pp. 7-24
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the performance overheads of prior policies. The proposed policy reduces leakage energy...
 
Dynamic Voltage Scaling in Multitier Web Servers with End-to-End Delay Control
Found in: IEEE Transactions on Computers
By Tibor Horvath, Tarek Abdelzaher, Kevin Skadron, Xue Liu
Issue Date:April 2007
pp. 444-458
The energy and cooling costs of Web server farms are among their main financial expenditures. This paper explores the benefits of dynamic voltage scaling (DVS) for power management in server farms. Unlike previous work, which addressed DVS on individual se...
 
Enhancing Energy Efficiency in Multi-tier Web Server Clusters via Prioritization
Found in: Parallel and Distributed Processing Symposium, International
By Tibor Horvath, Kevin Skadron, Tarek Abdelzaher
Issue Date:March 2007
pp. 319
This paper investigates the design issues and energy savings benefits of service prioritization in multi-tier web server clusters. In many services, classes of clients can be naturally assigned different priorities based on their performance requirements. ...
 
Improved Thermal Management with Reliability Banking
Found in: IEEE Micro
By Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron
Issue Date:November 2005
pp. 40-49
Most existing integrated circuit (IC) reliability models assume a uniform, typically worst-case, operating temperature, but temporal and spatial temperature variations affect expected device lifetime. As a result, design decisions and dynamic thermal manag...
 
Monitoring Temperature in FPGA based SoCs
Found in: Computer Design, International Conference on
By Siva Velusamy, Wei Huang, John Lach, Mircea Stan, Kevin Skadron
Issue Date:October 2005
pp. 634-640
<p>FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher ondie temperatures and local hotspots. Sophisticated packaging techniques have beco...
 
Analytical Model for Sensor Placement on Microprocessors
Found in: Computer Design, International Conference on
By Kyeong-Jae Lee, Kevin Skadron, Wei Huang
Issue Date:October 2005
pp. 24-30
<p>Thermal management in microprocessors has become a major design challenge in recent years. Thermal monitoring through hardware sensors is important, and these sensors must be carefully placed on the chip to account for thermal gradients. In this p...
 
Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors
Found in: Parallel and Distributed Processing Symposium, International
By Kyeong-Jae Lee, Kevin Skadron
Issue Date:April 2005
pp. 232a
As energy consumption in high-performance systems has increased, thermal management has become a big challenge. Providing a cost-effective and detailed temperature sensing mechanism is crucial to effectively employ a thermal management technique. Existing ...
 
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
Found in: High-Performance Computer Architecture, International Symposium on
By Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron
Issue Date:February 2005
pp. 71-82
Simultaneous multithreading (SMT) and chip multi-processing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are still poorly understood. This paper uses Turandot, PowerTimer, and HotSpot to...
 
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
Found in: Computer Design, International Conference on
By John Lach, Jason Brandon, Kevin Skadron
Issue Date:October 2004
pp. 144-150
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been developed to help reduce leakage in SRAM-based memory, in which the percent ...
 
Understanding the Energy Efficiency of Simultaneous Multithreading
Found in: Low Power Electronics and Design, International Symposium on
By Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
Issue Date:August 2004
pp. 44-49
Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of ...
 
Compact Thermal Modeling for Temperature-Aware Design
Found in: Design Automation Conference
By Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy
Issue Date:June 2004
pp. 878-883
Thermal design in sub-100nm technologies is one of the major challenges to the CAD community. In this paper, we first introduce the idea of temperature-aware design. We then propose a compact thermal model which can be integrated with modern CAD tools to a...
 
Power-Aware Branch Prediction: Characterization and Design
Found in: IEEE Transactions on Computers
By Dharmesh Parikh, Kevin Skadron, Yan Zhang, Mircea Stan
Issue Date:February 2004
pp. 168-186
<p><b>Abstract</b>—This paper uses Wattch and the SPEC 2000 integer and floating-point benchmarks to explore the role of branch predictor organization in power/energy/performance trade offs for processor design. Even though the direction ...
 
State-Preserving vs. Non-State-Preserving Leakage Control in Caches
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea Stan, Kevin Skadron
Issue Date:February 2004
pp. 10022
<p>This paper compares the effectiveness of state-preserving and non-state-preserving techniques for leakage control in caches by comparing drowsy cache and gated-V<sub>ss</sub> for data caches using 70nm technology parameters. To perform...
 
Hybrid Architectural Dynamic Thermal Management
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Kevin Skadron
Issue Date:February 2004
pp. 10010
When an application or external environmental conditions cause a chip?s cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power density on the chip to maintain safe operating temperatures. The challenge is that even ...
 
Power-aware QoS Management in Web Servers
Found in: Real-Time Systems Symposium, IEEE International
By Vivek Sharma, Arun Thomas, Tarek Abdelzaher, Kevin Skadron, Zhijian Lu
Issue Date:December 2003
pp. 63
Power management in data centers has become an increasingly important concern. Large server installations are designed to handle peak load, which may be significantly larger than in off-peak conditions. The increasing cost of energy consumption and cooling...
 
Guest Editors' Introduction: Power-Aware Computing
Found in: Computer
By Mircea R. Stan, Kevin Skadron
Issue Date:December 2003
pp. 35-38
<p>Performance, complexity, cost, and power tradeoffs have created exciting challenges and opportunities in the rapidly changing field of power-aware computing.</p>
 
Reducing Multimedia Decode Power using Feedback Control
Found in: Computer Design, International Conference on
By Zhijian Lu, John Lach, Mircea Stan, Kevin Skadron
Issue Date:October 2003
pp. 489
Despite recent advances, battery life continues to be a limiting factor in mobile multimedia systems. Significant energy savings can be achieved by adapting systems at run-time to match the execution requirements of different tasks. This paper introduces a...
 
Challenges in Computer Architecture Evaluation
Found in: Computer
By Kevin Skadron, Margaret Martonosi, David I. August, Mark D. Hill, David J. Lilja, Vijay S. Pai
Issue Date:August 2003
pp. 30-36
<p>Reasoning about today's tremendously complex computer systems is difficult and developing them is expensive. Detailed software simulations are thus essential for evaluating computer architecture ideas. Industry uses simulation extensively during p...
 
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
Found in: Computer Design, International Conference on
By Zhigang Hu, Philo Juang, Kevin Skadron, Douglas Clark, Margaret Martonosi
Issue Date:September 2002
pp. 442
<p>With technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and shou...
 
Implementing Decay Techniques using 4T Quasi-Static Memory Cells
Found in: IEEE Computer Architecture Letters
By Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Zhigang Hu, Margaret Martonosi, Douglas W. Clark
Issue Date:January 2002
pp. N/A
This paper proposes the use of four-transistor (4T) cacheand branch predictor array cell designs to address increasingworries regarding leakage power dissipation. While 4T designslose state when infrequently accessed, they have very lowleakage, smaller are...
 
Minimal Subset Evaluation : Rapid Warm-Up for Simulated Hardware State
Found in: Computer Design, International Conference on
By John W. Haskins Jr, Kevin Skadron
Issue Date:September 2001
pp. 0032
Abstract: This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fast-forwarding portion of processor simulations. Warm up is commonly used prior to full-detail simulation to avoid cold-sta...
 
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Kevin Skadron, Margaret Martonosi, Douglas W. Clark
Issue Date:October 2000
pp. 199
The need for accurate conditional-branch prediction is well known: mispredictions waste large numbers of cycles, inhibit out-of-order execution, and waste power on mis-speculated computation. Prior work on branch-predictor organization has focused mainly o...
 
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques
Found in: IEEE Transactions on Computers
By Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark
Issue Date:November 1999
pp. 1260-1281
<p><b>Abstract</b>—Design parameters interact in complex ways in modern processors, especially because out-of-order issue and decoupling buffers allow latencies to be overlapped. Trade-offs among instruction-window size, branch-prediction...
 
Design Issues and Tradeoffs for Write Buffers
Found in: High-Performance Computer Architecture, International Symposium on
By Kevin Skadron, Douglas W. Clark
Issue Date:February 1997
pp. 144
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer can cause processor stalls when it is full, when it contends with a cache miss...
 
The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches
Found in: SC Conference
By David Tarjan, Kevin Skadron
Issue Date:November 2010
pp. 1-10
Graphics Processing Units (GPUs) have recently emerged as a new platform for high performance, general-purpose computing. Because current GPUs employ deep multithreading to hide latency, they only have small, per-core caches to capture reuse and eliminate ...
 
Architecture implications of pads as a scarce resource
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Runjie Zhang,Ke Wang,Brett H. Meyer,Mircea R. Stan,Kevin Skadron
Issue Date:June 2014
pp. 373-384
Due to non-ideal technology scaling, delivering a stable supply voltage is increasingly challenging. Furthermore, competition for limited chip interface resources (i.e., C4 pads) between power supply and I/O, and the loss of such resources to electromigrat...
   
Real-world design and evaluation of compiler-managed GPU redundant multithreading
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Jack Wadden,Alexander Lyashevsky,Sudhanva Gurumurthi,Vilas Sridharan,Kevin Skadron
Issue Date:June 2014
pp. 73-84
Reliability for general purpose processing on the GPU (GPGPU) is becoming a weak link in the construction of reliable supercomputer systems. Because hardware protection is expensive to develop, requires dedicated on-chip resources, and is not portable acro...
   
Pannotia: Understanding irregular GPGPU graph applications
Found in: 2013 IEEE International Symposium on Workload Characterization (IISWC)
By Shuai Che,Bradford M. Beckmann,Steven K. Reinhardt,Kevin Skadron
Issue Date:September 2013
pp. 185-195
GPUs have become popular recently to accelerate general-purpose data-parallel applications. However, most existing work has focused on GPU-friendly applications with regular data structures and access patterns. While a few prior studies have shown that som...
   
Temperature-Aware Microarchitecture
Found in: Computer Architecture, International Symposium on
By Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan
Issue Date:June 2003
pp. 2
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package?s...
 
Load balancing in a changing world: dealing with heterogeneity and performance variability
Found in: Proceedings of the ACM International Conference on Computing Frontiers (CF '13)
By Kevin Skadron, Michael Boyer, Nuwan Jayasena, Shuai Che
Issue Date:May 2013
pp. 1-10
Fully utilizing the power of modern heterogeneous systems requires judiciously dividing work across all of the available computational devices. Existing approaches for partitioning work require offline training and generate fixed partitions that fail to re...
     
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