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Displaying 1-48 out of 48 total
Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
Found in: IEEE Design and Test of Computers
By Hong Li, Chuan Xu, Kaustav Banerjee
Issue Date:July 2010
pp. 20-31
<p>Editor's note:</p><p>Carbon nanotubes and graphene nanoribbons are two promising next-generation interconnect technologies. Electrical modeling and performance analysis have demonstrated the superiority of these emerging technologies c...
 
Statistical modeling of metal-gate Work-Function Variability in emerging device technologies and implications for circuit design
Found in: Computer-Aided Design, International Conference on
By Hamed Dadgour, Vivek De, Kaustav Banerjee
Issue Date:November 2008
pp. 270-277
For the first time, a new source of random threshold voltage (V<inf>th</inf>) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of v...
 
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends
Found in: VLSI Design, International Conference on
By Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
Issue Date:January 2007
pp. 8
<p>The increasing complexity of Systems-on-Chip (SoCs) has led to the critical ?design productivity gap? problem. Several strategies are being employed to cope with this problem, including an IP-based design flow, as well as platform-based designs fo...
   
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
Found in: Computer Design, International Conference on
By Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
Issue Date:October 2005
pp. 411-416
<p>As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine ...
 
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
Found in: Quality Electronic Design, International Symposium on
By Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
Issue Date:March 2005
pp. 346-351
This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the import...
 
A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
Found in: Low Power Electronics and Design, International Symposium on
By Songqing Zhang, Vineet Wason, Kaustav Banerjee
Issue Date:August 2004
pp. 156-161
This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this ...
 
Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
Found in: Design Automation Conference
By Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
Issue Date:June 2004
pp. 884-887
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (V{dd}) and threshold (V{th}) volta...
 
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
Found in: Computer-Aided Design, International Conference on
By Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian Mihai Ionescu
Issue Date:November 2003
pp. 497
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown to be applicable in both digital and analog domains. ...
 
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design
Found in: Computer-Aided Design, International Conference on
By Kaustav Banerjee, Michel Declercq, Adil Koukab
Issue Date:November 2002
pp. 309-316
The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a su...
 
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
Found in: Computer-Aided Design, International Conference on
By Kaustav Banerjee, Amit Mehrotra
Issue Date:November 2001
pp. 158
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. This paper presents for the first time a rigorous coupled analysis of AC elect...
 
Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
Found in: Computer-Aided Design, International Conference on
By Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
Issue Date:November 2001
pp. 44
This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperature-dependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are prov...
 
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
Found in: Design Automation Conference
By Amit Mehrotra, Kaustav Banerjee
Issue Date:June 2001
pp. 798-803
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inducta...
 
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
Found in: Design Automation Conference
By Kaustav Banerjee, Lukas P. P. P. van Ginneken, Massoud Pedram, Amir H. Ajami
Issue Date:June 2001
pp. 567-572
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to non-un...
 
Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
Found in: Design Automation Conference
By Kaustav Banerjee, Amit Mehrotra, Krishna C. Saraswat, Shukri J. Souri
Issue Date:June 2000
pp. 213-220
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to...
 
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Issue Date:March 2008
pp. 426-431
We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) ...
 
3D Integration for Introspection
Found in: IEEE Micro
By Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
Issue Date:January 2007
pp. 77-83
In today's complex processors, specialized profiling and introspection hardware would be incredibly beneficial to software developers, but most proposals for its addition would increase the cost of every die manufactured. Modular,
 
Tutorial 1: Emerging Technologies for VLSI Design
Found in: Quality Electronic Design, International Symposium on
By Rajiv Joshi, Kaustav Banerjee, Andre DeHon
Issue Date:March 2006
pp. 4
This tutorial discusses emerging technologie. We will focus on three major components.
   
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
Found in: Quality Electronic Design, International Symposium on
By Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
Issue Date:March 2004
pp. 259-264
This paper introduces a new comprehensive analytical capacitance model for nanoscale architectures based on nanoscale metallic/semiconducting dots. The model takes into account a detailed charge interaction of the components and shows their implications on...
 
Power Supply Optimization in sub-130 nm Leakage Dominant Technologies
Found in: Quality Electronic Design, International Symposium on
By Man L Mui, Kaustav Banerjee, Amit Mehrotra
Issue Date:March 2004
pp. 409-414
In this paper we present a methodology for systematically optimizing the power supply voltage for maximizing the performance of VLSI circuits in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purp...
 
Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
Found in: Quality Electronic Design, International Symposium on
By Amir H. Ajami, Kaustav Banerjee, Amit Mehrotra, Massoud Pedram
Issue Date:March 2003
pp. 35
This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconne...
 
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
Found in: Quality Electronic Design, International Symposium on
By Choshu Ito, Kaustav Banerjee, Robert W. Dutton
Issue Date:March 2001
pp. 117
Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high frequency and RF circuits. This work presents for the first time, an s-parameter based analysis of the performance of RF circuits with various ESD protec...
 
Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
Found in: Design Automation Conference
By Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
Issue Date:June 2002
pp. 88
In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics a...
 
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
Found in: Computer-Aided Design, International Conference on
By Ting-Yen Chiang, Kaustav Banerjee, Krishna C. Saraswat
Issue Date:November 2001
pp. 165
This paper presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low-k interconnects under steady-state and transient stress condi...
 
On Thermal Effects in Deep Sub-Micron VLSI Interconnects
Found in: Design Automation Conference
By Kaustav Banerjee, Amit Mehrotra, Alberto Sangiovanni-Vincentelli, Chenming Hu
Issue Date:June 1999
pp. 885-891
This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling ef...
 
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs
Found in: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (ISLPED '10)
By Hamed Dadgour, Kaustav Banerjee, Muhammad M. Hussain
Issue Date:August 2010
pp. 7-12
Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, later...
     
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Casey Smith, Hamed F. Dadgour, Kaustav Banerjee, Muhammad M. Hussain
Issue Date:June 2010
pp. 893-896
Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally-actuated dou...
     
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies
Found in: Proceedings of the 2009 International Conference on Computer-Aided Design (ICCAD '09)
By Alina Deutsch, Barry J. Rubin, Chuan Xu, Howard Smith, Kaustav Banerjee, Lijun Jiang, Seshadri K. Kolluri
Issue Date:November 2009
pp. 658-665
Accurate and fast estimation of VLSI interconnect thermal profiles has become critically important to estimate their impact on circuit/system performance and reliability, which is necessary for reducing product development time and achieving first-pass sil...
     
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization
Found in: Proceedings of the 2009 International Conference on Computer-Aided Design (ICCAD '09)
By Kaustav Banerjee, Kazuhiko Endo, Seid Hadi Rasouli
Issue Date:November 2009
pp. 505-512
FinFET is considered as the most likely candidate to substitute bulk CMOS technology. FinFET-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect)...
     
Graphene based nanomaterials for VLSI interconnect and energy-storage applications
Found in: Proceedings of the 11th international workshop on System level interconnect prediction (SLIP '09)
By Kaustav Banerjee
Issue Date:July 2009
pp. 1-2
As IC feature sizes continue to be scaled below 45 nanometer, copper wires exhibit significant "size effects" resulting in a sharp rise in their resistivity, which, in turn, has adverse impact both on their performance as well as reliability--in the form o...
     
Graphene based transistors: physics, status and future perspectives
Found in: Proceedings of the 2009 international symposium on Physical design (ISPD '09)
By Chaitanya Kshirsagar, Kaustav Banerjee, S. Hadi Rasouli, Yasin Khatami
Issue Date:March 2009
pp. 1-2
Graphene is a single-atom thick layer of graphite, which is one of the well known allotropes of carbon. While Graphene is a 2-D material, it can be either rolled-up to form carbon nanotubes (CNT) or simply patterned to form graphene nano-ribbons (GNR), whi...
     
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs
Found in: Proceedings of the 45th annual conference on Design automation (DAC '08)
By Chaitanya Kshirsagar, Kaustav Banerjee, Mohamed N. El-Zeftawi
Issue Date:June 2008
pp. 1-30
Intrinsic and parasitic capacitances play an important role in determining the high-frequency RF performance of devices. Recently, a new type of carbon nanotube field effect transistor (CNFET) based on tunneling principle has been proposed, which shows imp...
     
High-frequency mutual impedance extraction of VLSI interconnects in the presence of a multi-layer conducting substrate
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Kaustav Banerjee, Navin Srivastava, Roberto Suaya
Issue Date:March 2008
pp. 1-30
We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) ...
     
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Hamed F. Dadgour, Kaustav Banerjee
Issue Date:June 2007
pp. 306-311
Integration of nano-electro-mechanical switches (NEMS) with CMOS technology has been proposed to exploit both near zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches ...
     
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Kaustav Banerjee, Sheng-Chih Lin
Issue Date:November 2006
pp. 568-574
As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are beginning to impact VLSI design. Moreover, elevated substrate (junction or die...
     
Introspective 3D chips
Found in: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS-XII)
By Banit Agrawal, Kaustav Banerjee, Navin Srivastava, Shashidhar Mysore, Sheng-Chih Lin, Tim Sherwood
Issue Date:October 2006
pp. 109-es
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexity of modern systems, software developers are increasingly dependent on specia...
     
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Banit Agrawal, Gian Luca Loi, Kaustav Banerjee, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood
Issue Date:July 2006
pp. 991-996
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can poten...
     
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Hamed F. Dadgour, Kaustav Banerjee, Rajiv V. Joshi
Issue Date:July 2006
pp. 977-982
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (N...
     
Are carbon nanotubes the future of VLSI interconnections?
Found in: Proceedings of the 43rd annual conference on Design automation (DAC '06)
By Kaustav Banerjee, Navin Srivastava
Issue Date:July 2006
pp. 809-814
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates tha...
     
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems
Found in: Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC '06)
By Kaustav Banerjee, Navin Srivastava, Sheng-Chih Lin
Issue Date:January 2006
pp. 223-230
Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This pa...
     
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations
Found in: Proceedings of the 2004 international symposium on Low power electronics and design (ISLPED '04)
By Kaustav Banerjee, Songqing Zhang, Vineet Wason
Issue Date:August 2004
pp. 156-161
This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this ...
     
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design
Found in: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design (ICCAD '02)
By Adil Koukab, Kaustav Banerjee, Michel Declercq
Issue Date:November 2002
pp. 309-316
The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a su...
     
Few electron devices: towards hybrid CMOS-SET integrated circuits
Found in: Proceedings of the 39th conference on Design automation (DAC '02)
By Adrian M. Ionescu, Jacques Gautier, Kaustav Banerjee, Michel J. Declercq, Santanu Mahapatra
Issue Date:June 2002
pp. 88-93
In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics a...
     
Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects
Found in: Proceedings of the 38th conference on Design automation (DAC '01)
By Amit Mehrotra, Kaustav Banerjee
Issue Date:June 2001
pp. 798-803
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inducta...
     
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Found in: Proceedings of the 38th conference on Design automation (DAC '01)
By Amir H. Ajami, Kaustav Banerjee, Lukas P. P. P. van Ginneken, Massoud Pedram
Issue Date:June 2001
pp. 567-572
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to non-u...
     
Analysis and optimization of thermal issues in high-performance VLSI
Found in: Proceedings of the 2001 international symposium on Physical design (ISPD '01)
By Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
Issue Date:April 2001
pp. 230-237
This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and e...
     
Multiple Si layer ICs: motivation, performance analysis, and design implications
Found in: Proceedings of the 37th conference on Design automation (DAC '00)
By Amit Mehrotra, Kaustav Banerjee, Krishna C. Saraswat, Shukri J. Souri
Issue Date:June 2000
pp. 213-220
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to...
     
Performance analysis and technology of 3-D ICs
Found in: Proceedings of the 2000 international workshop on System-level interconnect prediction (SLIP '00)
By Kaustav Banerjee, Krishna C. Saraswat, Pawan Kapur, Shukri J. Souri
Issue Date:April 2000
pp. 85-90
The importance of integration in programming environments is well known. Perhaps the easiest way to build an integrated system is to build a closed system; the designers of the system can use whatever ad hoc techniques are available to make the pieces they...
     
On thermal effects in deep sub-micron VLSI interconnects
Found in: Proceedings of the 36th ACM/IEEE conference on Design automation conference (DAC '99)
By Alberto Sangiovanni-Vincentelli, Amit Mehrotra, Chenming Hu, Kaustav Banerjee
Issue Date:June 1999
pp. 885-891
Due to a patent dispute, full text of this article is not availableat this time.
     
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