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Displaying 1-17 out of 17 total
Handling Nondeterminism in Logic Simulation So That Your Waveform Can Be Trusted Again
Found in: IEEE Design and Test of Computers
By Kai-hui Chang,Hong-Zu Chou,Haiqian Yu,Dylan Dobbyn,Sy-Yen Kuo
Publication Date: June 2011
pp. N/A
The increasing complexity of integrated circuits pushes for more aggressive design optimizations, such as resetting only part of design registers, that can leave some registers in nondeterministic (X) states. Such Xs may invalidate the correctness of logic...
 
Applying verification intention for design customization via property mining under constrained testbenches
Found in: Computer Design, International Conference on
By Chih-Neng Chung,Chia-Wei Chang,Kai-Hui Chang,Sy-Yen Kuo
Issue Date:October 2011
pp. 84-89
Most synthesis tools perform optimizations based on the design itself and do not utilize the information present in the verification environment. Not using such information greatly limits the optimization capabilities of synthesis tools, which is especiall...
 
Formal reset recovery slack calculation at the register transfer level
Found in: 2011 Design, Automation & Test in Europe
By Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo
Issue Date:March 2011
pp. 1-4
Reset is one of the most important signals in many designs. Since reset is typically not timing critical, it is handled at late physical design stages. However, the large fanout of reset and the lack of routing resources at these stages can create variant ...
   
RTL analysis and modifications for improving at-speed test
Found in: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
By Kai-Hui Chang, Hong-Zu Chou,I. L. Markov
Issue Date:March 2012
pp. 400-405
At-speed testing is increasingly important at recent technology nodes due to growing uncertainty in chip manufacturing. However, at-speed fault coverage and test-efficacy suffer when tests are not robust. Since Automatic Test Pattern Generation (ATPG) is t...
 
Parallel Logic Simulation: Myth or Reality?
Found in: Computer
By Kai-hui Chang,Chris Browy
Issue Date:April 2012
pp. 67-73
The rapid adoption of multiprocessor computers creates a perfect environment for parallel EDA algorithms. Among various EDA applications, parallel logic simulation seems the most promising. As processors become faster and designs grow larger, better perfor...
 
Incremental Verification with Error Detection, Diagnosis, and Visualization
Found in: IEEE Design and Test of Computers
By Kai-hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
Issue Date:March 2009
pp. 34-43
<p>Invers is a fast incremental-verification system for physical-synthesis optimization that includes capabilities for error detection, diagnosis, and visualization. Using a new metric called the similarity factor, Invers can help engineers identify ...
 
Automating Postsilicon Debugging and Repair
Found in: Computer
By Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
Issue Date:July 2008
pp. 47-54
Due to increasing semiconductor design complexity, more errors are escaping presilicon verification and being discovered only after manufacturing. As an alternative to traditional manual chip repair, the authors propose the FogClear methodology, which auto...
 
Automatic error diagnosis and correction for RTL designs
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By Kai-hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov
Issue Date:November 2007
pp. 65-72
Recent improvements in design verification strive to automate the error-detection process and greatly enhance engineers’ ability to detect functional errors. However, the process of diagnosing the cause of these errors and fixing them remains difficult and...
 
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization
Found in: Quality Electronic Design, International Symposium on
By Kai-hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
Issue Date:March 2007
pp. 487-494
Dramatic increases in design complexity and advances in IC manufacturing technology affect all aspects of circuit performance and functional correctness. As interconnect increasingly dominates delay and power at the latest technology nodes, much effort is ...
 
Fixing Design Errors with Counterexamples and Resynthesis
Found in: Asia and South Pacific Design Automation Conference
By Kai-Hui Chang, I.L. Markov, V. Bertacco
Issue Date:January 2007
pp. 944-949
In this work we propose a new error-correction framework, called CoRe, which uses counterexamples, or bug traces, generated in verification to automatically correct errors in digital designs. CoRe is powered by two innovative resynthesis techniques, goal-d...
 
Safe Delay Optimization for Physical Synthesis
Found in: Asia and South Pacific Design Automation Conference
By Kai-hui Chang, I.L. Markov, V. Bertacco
Issue Date:January 2007
pp. 628-633
Physical synthesis is a relatively young field in electronic design automation. Many published optimizations for physical synthesis end up hurting the final result, often by neglecting important physical aspects of the layout, such as long wires or routing...
 
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries
Found in: Computer-Aided Design, International Conference on
By Kai-hui Chang, I.L. Markov, V. Bertacco
Issue Date:May 2005
pp. 56-63
Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common benchmarks. However, to be competitive, modern circuit optimizations must use physical and logic information simultaneously. In this work...
 
Simulation-based bug trace minimization with BMC-based refinement
Found in: Computer-Aided Design, International Conference on
By Kai-hui Chang, V. Bertacco, I.L. Markov
Issue Date:May 2005
pp. 1045-1051
Finding the cause of a bug can be one of the most time-consuming activities in design verification. This is particularly true in the case of bugs discovered in the context of a random simulation- based methodology, where bug traces, or counter-examples, ma...
 
Enhancing bug hunting using high-level symbolic simulation
Found in: Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLSVLSI '09)
By Ching-Sung Yang, Hong-Zu Chou, I-Hui Lin, Kai-Hui Chang, Sy-Yen Kuo
Issue Date:May 2009
pp. 375-376
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Therefore, it is imperative to find design bugs as early as possible. The first de...
     
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
Issue Date:July 2009
pp. 412-415
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle such conditions accurately at the behavior and register transfer levels, which is ...
     
Reap what you sow: spare cells for post-silicon metal fix
Found in: Proceedings of the 2008 international symposium on Physical design (ISPD '08)
By Igor L. Markov, Kai-hui Chang, Valeria Bertacco
Issue Date:April 2008
pp. 4-4
Post-silicon validation has recently become a major bottleneck in IC design. Several high profile IC designs have been taped-out with latent bugs, and forced the manufacturers to resort to additional design revisions. Such changes can be applied through me...
     
Postplacement rewiring by exhaustive search for functional symmetries
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Igor L. Markov, Kai-Hui Chang, Valeria Bertacco
Issue Date:August 2007
pp. 1-21
We propose two new algorithms for rewiring: a postplacement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. In the first algorithm, we extract small subcircuits consisting of several gates from t...
     
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