Search For:

Displaying 1-30 out of 30 total
Preventing IC Piracy Using Reconfigurable Logic Barriers
Found in: IEEE Design and Test of Computers
By Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno
Issue Date:January 2010
pp. 66-75
<p>Editor's note:</p><p>Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the ob...
 
Securing Multimedia Content Using Joint Compression and Encryption
Found in: IEEE MultiMedia
By Amit Pande,Prasant Mohapatra,Joseph Zambreno
Issue Date:October 2013
pp. 50-61
Algorithmic parameterization and hardware architectures can ensure secure transmission of multimedia data in resource-constrained environments such as wireless video surveillance networks, telemedicine frameworks for distant health care support in rural ar...
 
Reduce, Reuse, Recycle (R 3 ): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms
Found in: 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
By Kevin Townsend,Joseph Zambreno
Issue Date:June 2013
pp. 185-191
Sparse Matrix Vector Multiplication (SpMV) is an important computational kernel in many scientific computing applications. Pipelining multiply-accumulate operations shifts SpMV from a computationally bounded kernel to an I/O bounded kernel. In this paper, ...
 
A multi-faceted approach to FPGA-based Trojan circuit detection
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Michael Patterson,Aaron Mills,Ryan Scheel,Julie Tillman,Evan Dye,Joseph Zambreno
Issue Date:April 2013
pp. 1-4
Three general approaches to detecting Trojans embedded in FPGA circuits were explored in the context of the 2012 CSAW Embededed Systems Challenge: functional testing, power analysis, and direct analysis of the bitfile. These tests were used to classify a s...
 
Design and evaluation of a delay-based FPGA Physically Unclonable Function
Found in: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
By Aaron Mills,Sudhanshu Vyas,Michael Patterson,Christopher Sabotta,Phillip Jones,Joseph Zambreno
Issue Date:September 2012
pp. 143-146
A new Physically Unclonable Function (PUF) variant was developed on an FPGA, and its quality evaluated. It is conceptually similar to PUFs developed using standard SRAM cells, except it utilizes general FPGA reconfigurable fabric, which offers several adva...
 
Using Chaotic Maps for Encrypting Image and Video Content
Found in: Multimedia, International Symposium on
By Amit Pande,Prasant Mohapatra,Joseph Zambreno
Issue Date:December 2011
pp. 171-178
Arithmetic Coding (AC) is widely used for the entropy coding of text and multimedia data. It involves recursive partitioning of the range [0,1) in accordance with the relative probabilities of occurrence of the input symbols. In this paper, we present a da...
 
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection
Found in: Computer Design, International Conference on
By Justin Rilling,David Graziano,Jamin Hitchcock,Tim Meyer,Xinying Wang,Phillip Jones,Joseph Zambreno
Issue Date:October 2011
pp. 289-292
Ring oscillators are commonly used as a locking mechanism that binds a hardware design to a specific area of silicon within an integrated circuit (IC). This locking mechanism can be used to detect malicious modifications to the hardware design, also known ...
 
Architectures for Simultaneous Coding and Encryption Using Chaotic Maps
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Amit Pande, Joseph Zambreno, Prasant Mohapatra
Issue Date:July 2011
pp. 351-352
In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit fixed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher tha...
 
Teaching graphics processing and architecture using a hardware prototyping approach
Found in: Microelectronics Systems Education, IEEE International Conference on
By Michael Steffen,Phillip Jones,Joseph Zambreno
Issue Date:June 2011
pp. 13-16
Since its introduction over two decades ago, graphics hardware has continued to evolve to improve rendering performance and increase programmability. While most undergraduate courses in computer graphics focus on rendering algorithms and programming APIs, ...
 
Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining
Found in: IEEE Transactions on Parallel and Distributed Systems
By Song Sun, Joseph Zambreno
Issue Date:September 2011
pp. 1497-1505
Frequent pattern mining algorithms are designed to find commonly occurring sets in databases. This class of algorithms is typically very memory intensive, leading to prohibitive runtimes on large databases. A class of reconfigurable architectures has been ...
 
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Michael Steffen, Joseph Zambreno
Issue Date:December 2010
pp. 237-248
Wide Single Instruction, Multiple Thread (SIMT)architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application kernel. Individual thread branching is supported by executing all control flow pa...
 
A hardware pipeline for accelerating ray traversal algorithms on streaming processors
Found in: Application Specific Processors, Symposium on
By Michael Steffen, Joseph Zambreno
Issue Date:June 2010
pp. 22-29
Ray Tracing is a graphics rendering method that uses rays to trace the path of light in a computer model. To accelerate the processing of rays, scenes are typically compiled into smaller spatial boxes using a tree structure and rays then traverse the tree ...
 
A Reconfigurable Architecture for Secure Multimedia Delivery
Found in: VLSI Design, International Conference on
By Amit Pande, Joseph Zambreno
Issue Date:January 2010
pp. 258-263
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform DWT). This parameterized construction promises multimedia encryption and is al...
 
Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems
Found in: Computational Science and Engineering, IEEE International Conference on
By Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
Issue Date:August 2009
pp. 830-836
Much of modern software development consists of assembling together existing software components and writing the glue code that integrates them into a unified application. The term COTS-Based System (CBS) is often used to describe such applications, for wh...
 
Architectural Support for Automated Software Attack Detection, Recovery, and Prevention
Found in: Computational Science and Engineering, IEEE International Conference on
By Jesse Sathre, Alex Baumgarten, Joseph Zambreno
Issue Date:August 2009
pp. 254-261
Attacks on software systems are an increasingly serious problem from an economic and security standpoint. Many techniques have been proposed ranging from simple compiler modifications to full-scale re-engineering of computer systems architecture aimed at a...
 
Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores
Found in: Computational Science and Engineering, IEEE International Conference on
By Amit Pande, Joseph Zambreno
Issue Date:August 2009
pp. 915-920
In this paper we present the design of a novelembedded processor architecture (which we call a μ-core) that makes use of a reconfigurable ALU. This core serves as the basis of custom 2-dimensional array architectures that can be used to accelerate algorith...
 
An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Amit Pande, Joseph Zambreno
Issue Date:May 2009
pp. 85-90
This paper introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parametrized construction of the Discrete Wavelet Transform (DWT) compression block is used to introduce a free parameter in the desig...
 
A Reconfigurable Platform for Frequent Pattern Mining
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Song Sun, Michael Steffen, Joseph Zambreno
Issue Date:December 2008
pp. 55-60
In this paper, a new hardware architecture for frequent pattern mining based on a systolic tree structure is proposed. The goal of this architecture is to mimic the internal memory layout of the original FP-growth algorithm while achieving a much higher th...
 
Evaluating the effects of cache redundancy on profit
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Abhishek Das, Berkin Ozisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Choudhary
Issue Date:November 2008
pp. 388-398
Previous works in computer architecture have mostly neglected revenue and/or profit, key factors driving any design decision. In this paper, we evaluate architectural techniques to optimize for revenue/profit. The continual trend of technology scaling and ...
 
Microarchitectures for Managing Chip Revenues under Process Variations
Found in: IEEE Computer Architecture Letters
By Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Choudhary
Issue Date:January 2008
pp. 5-8
As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the effects of process variationson critical path delay and chip yields have amplified. A commonconcept to remedy the effects of variation is speed-binning, bywhich chips fro...
 
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok Choudhary
Issue Date:March 2008
pp. 1160-1165
Modern Network Intrsuion Detection Systems (NIDSs) use anomaly detection to capture malicious attacks. Since such connections are described by large set of dimensions, processing these huge amounts of network data becomes extremely slow. To solve this time...
 
Microarchitectures for Managing Chip Revenues under Process Variations
Found in: IEEE Computer Architecture Letters
By Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Choudhary
Issue Date:July 2007
pp. 29-32
As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the effects of process variationson critical path delay and chip yields have amplified. A commonconcept to remedy the effects of variation is speed-binning, bywhich chips fro...
 
Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Joseph Zambreno, Dan Honbo, Alok Choudhary
Issue Date:April 2005
pp. 333-334
In recent years, reconfigurable technology has emerged as a popular choice for implementing various types of cryptographic functions. Nevertheless, an insufficient amount effort has been placed into fully exploiting the tremendous amounts of parallelism in...
   
Flexible Software Protection Using Hardware/Software Codesign Techniques
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Joseph Zambreno, Alok Choudhary, Rahul Simha, Bhagirath Narahari
Issue Date:February 2004
pp. 10636
A strong level of trust in the software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of software protection attempts to address the key steps used by hackers in attacking a so...
 
Hardware architectural support for control systems and sensor processing
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Adwait Gupte, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones, Ron K. Cytron, Sudhanshu Vyas
Issue Date:September 2013
pp. 1-25
The field of modern control theory and the systems used to implement these controls have shown rapid development over the last 50 years. It was often the case that those developing control algorithms could assume the computing medium was solely dedicated t...
     
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Amit Pande, Joseph Zambreno
Issue Date:March 2012
pp. 1-26
Many modern computing applications have been enabled through the use of real-time multimedia processing. While several hardware architectures have been proposed in the research literature to support such primitives, these fail to address applications whose...
     
Hardware-enforced fine-grained isolation of untrusted code
Found in: Proceedings of the first ACM workshop on Secure execution of untrusted code (SecuCode '09)
By Bhagirath Narahari, Eugen Leontie, Gedare Bloom, Joseph Zambreno, Rahul Simha
Issue Date:November 2009
pp. 11-18
We present a novel combination of hardware (architecture) and software (compiler) techniques to support the safe execution of untrusted code. While other efforts focus on isolating processes, our approach isolates code and data at a function (as in, C func...
     
An efficient FPGA implementation of principle component analysis based network intrusion detection system
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By Abhishek Das, Alok Choudhary, Gokhan Memik, Joseph Zambreno, Sanchit Misra, Sumeet Joshi
Issue Date:March 2008
pp. 1-30
Modern Network Intrsuion Detection Systems (NIDSs) use anomaly detection to capture malicious attacks. Since such connections are described by large set of dimensions, processing these huge amounts of network data becomes extremely slow. To solve this time...
     
Interactive presentation: An FPGA implementation of decision tree classification
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '07)
By Alok Choudhary, Daniel Honbo, Gokhan Memik, Joseph Zambreno, Ramanathan Narayanan
Issue Date:April 2007
pp. 189-194
Data mining techniques are a rapidly emerging class of applications that have widespread use in several fields. One important problem in data mining is Classification, which is the task of assigning objects to one of several predefined categories. Among th...
     
SAFE-OPS: An approach to embedded software security
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Alok Choudhary, Bhagi Narahari, Joseph Zambreno, Nasir Memon, Rahul Simha
Issue Date:February 2005
pp. 189-210
The new-found ubiquity of embedded processors in consumer and industrial applications brings with it an intensified focus on security, as a strong level of trust in the system software is crucial to their widespread deployment. The growing area of software...
     
 1