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Displaying 1-22 out of 22 total
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Found in: Dependable Systems and Networks, International Conference on
By Christopher LaFrieda, Engin Ipek, Jose F. Martinez, Rajit Manohar
Issue Date:June 2007
pp. 317-326
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Existing fault-tolerant CMP proposals that implement dual modular redundancy (DMR...
 
Synchronization in a Wireless Sensor Network Designed for Surveillance Applications
Found in: Wireless and Mobile Communications, International Conference on
By Jose A. Sánchez Fernández, Ana B. García Hernando, José F. Martínez Ortega, Lourdes López Santidrián
Issue Date:August 2009
pp. 369-372
System dynamics and algebraic graph theory provide the mathematical framework to understand the dynamical and topological features of complex networks, among them the synchronization properties of wireless sensor networks (WSN), a far from trivial subject ...
 
Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
Issue Date:November 2002
pp. 3
This paper presents CHeckpointed Early Resource RecYcling (Cherry), a hybrid mode of execution based on ROB and checkpointing that decouples resource recycling and instruction retirement. Resources are recycled early, resulting in a more efficient utilizat...
 
Editorial
Found in: IEEE Computer Architecture Letters
By Jose F. Martinez
Issue Date:July 2013
pp. 37-38
No summary available.
 
A Message from the New Editor-in-Chief and Introduction of New Associate Editors
Found in: IEEE Computer Architecture Letters
By Jose F. Martinez
Issue Date:January 2013
pp. 2-4
The incoming Editor-in-Chief states that his goal during his tenure with IEEE Computer Architecture Letters (CAL) will be to further increase its visibility in our research community, and to attract more submissions from computer architecture leaders. The
 
Dynamic Multicore Resource Management: A Machine Learning Approach
Found in: IEEE Micro
By José F. Martínez, Engin İpek
Issue Date:September 2009
pp. 8-17
<p>A machine learning approach to multicore resource management produces self-optimizing on-chip hardware agents capable of learning, planning, and continuously adapting to changing workload demands. This results in more efficient and flexible manage...
 
A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity
Found in: Parallel and Distributed Processing Symposium, International
By Engin Ipek, Meyrem Kirman, Nevin Kirman, Jose F. Martinez
Issue Date:March 2007
pp. 338
We present core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at run time by applicati...
 
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jose F. Martinez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
Issue Date:December 2006
pp. 492-503
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects. In this paper, we investigate the int...
 
Security Framework for DPWS Compliant Devices
Found in: Emerging Security Information, Systems, and Technologies, The International Conference on
By Vicente Hernández, Lourdes López, Oscar Prieto, José-F. Martínez, Ana-B. García, Antonio Da Silva
Issue Date:June 2009
pp. 87-92
The DPWS (Devices Profile for Web Services) specification enables devices, including small-scale ones, to be integrated seamlessly in a service oriented architecture (SOA). Complex enterprise applications are able to access devices functionalities in a Web...
 
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Ramazan Bitirgen, Engin Ipek, Jose F. Martinez
Issue Date:November 2008
pp. 318-329
Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although several proposals that address the management of a single microarchitectural resource...
 
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
Found in: Computer Architecture, International Symposium on
By Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana
Issue Date:June 2008
pp. 39-50
Efficiently utilizing off-chip DRAM bandwidth is a critical issuein designing cost-effective, high-performance chip multiprocessors(CMPs). Conventional memory controllers deliver relativelylow performance in part because they often employ fixed,rigid acces...
 
On-Chip Optical Technology in Future Bus-Based Multicore Designs
Found in: IEEE Micro
By Nevin Kırman, Meyrem Kırman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
Issue Date:January 2007
pp. 56-66
This work investigates the integration of CMOS-compatible optical technology to on-chip coherent buses for future CMPs. The analysis results in a hierarchical optoelectrical bus that exploits the advantages of optical technology while abiding by projected ...
 
Checkpointed Early Load Retirement
Found in: High-Performance Computer Architecture, International Symposium on
By Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
Issue Date:February 2005
pp. 16-27
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions, they also prevent other instructions from moving through the in-order reorder buf...
 
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
Found in: High-Performance Computer Architecture, International Symposium on
By Jian Li, José F. Martínez, Michael C. Huang
Issue Date:February 2004
pp. 14
<p>Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative nature of the computation, the most energy-efficient execution in each...
 
Speculative Synchronization: Programmability and Performance for Parallel Codes
Found in: IEEE Micro
By José F. Martínez, Josep Torrellas
Issue Date:November 2003
pp. 126-134
<p>Proper synchronization is vital to ensuring that parallel applications execute correctly. A common practice is to place synchronization conservatively so as to produce simpler code in less time. Unfortunately, this practice frequently results in s...
 
A Case for Resource-conscious Out-of-order Processors
Found in: IEEE Computer Architecture Letters
By Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
Issue Date:January 2003
pp. N/A
Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of t...
 
Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors
Found in: Computer Architecture, International Symposium on
By José F. Martínez, Josep Torrellas, Marcelo Cintra
Issue Date:June 2000
pp. 13
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited ...
 
MORSE: Multi-objective reconfigurable self-optimizing memory scheduler
Found in: High-Performance Computer Architecture, International Symposium on
By Janani Mukundan,Jose F. Martinez
Issue Date:February 2012
pp. 1-12
We propose a systematic and general approach to designing self-optimizing memory schedulers that can target arbitrary figures of merit (e.g., performance, throughput, energy, fairness). Using our framework, we instantiate three memory schedulers that targe...
 
XML Schema Based Faultset Definition to Improve Faults Injection Tools Interoperability
Found in: Dependability of Computer Systems, International Conference on
By Antonio da Silva, José F. Martínez, Lourdes López, Ana B. García, Vicente Hernández
Issue Date:June 2008
pp. 39-46
This paper describes an XML schema formalization approach for the definition of basic fault sets which specify memory and/or register value corruption in microprocessor-based systems. SWIFI (Software Implemented Fault Injection) tools use fault injectors t...
 
Core fusion: accommodating software diversity in chip multiprocessors
Found in: Proceedings of the 34th annual international symposium on Computer architecture (ISCA '07)
By Engin Ipek, Jose F. Martinez, Meyrem Kirman, Nevin Kirman
Issue Date:June 2007
pp. 186-197
This paper presents core fusion, a reconfigurable chip multiprocessor(CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at run time by a...
     
QoS in wireless sensor networks: survey and approach
Found in: Proceedings of the 2007 Euro American conference on Telematics and information systems (EATIS '07)
By Ana-B Garci, Antonio Dasilva, Ivan Corredor, Jose-F Martinez, Lourdes Lopez, Vicente Hernandez
Issue Date:May 2007
pp. 19-23
A wireless sensor network (WSN) is a computer wireless network composed of spatially distributed and autonomous tiny nodes -- smart dust sensors, motes -, which cooperatively monitor physical or environmental conditions. Nowadays these kinds of networks su...
     
Speculative synchronization: applying thread-level speculation to explicitly parallel applications
Found in: Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X) (ASPLOS '02)
By Jose F. Martinez, Josep Torrellas
Issue Date:October 2002
pp. 205-209
Barriers, locks, and flags are synchronizing operations widely used programmers and parallelizing compilers to produce race-free parallel programs. Often times, these operations are placed suboptimally, either because of conservative assumptions about the ...
     
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