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Displaying 1-50 out of 67 total
Keynote talk by Dr. Jean-Luc Gaudiot: Fighting Amdahl's law in many-core and GPU parallel architectures with value prediction
Found in: 2011 9th IEEE/ACS International Conference on Computer Systems and Applications (AICCSA)
By Jean-Luc Gaudiot
Issue Date:December 2011
pp. 1
Summary form only given. The next grail sought by HPC community is the exascale, 100 times the current scale. This target will not be reached easily as many challenges are uprising. The first challenge, the Energy consumption, has become a strict constrain...
   
Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture
Found in: 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)
By Jed Kao-Tung Chang,Chen Liu,Jean-Luc Gaudiot
Issue Date:May 2013
pp. 2035-2044
Data encryption/decryption has become an essential part of modern information systems. However, executing these cryptography algorithms introduces high overhead issues for performance, power, and hardware cost. Through profiling work, we found that cryptog...
 
Parallel Discrete-Event Simulation
Found in: IEEE Design and Test of Computers
By Walid Najjar, Jean-luc Jezouin, Jean-luc Gaudiot
Issue Date:November 1987
pp. 41-44
The availability of commercial multiprocessors gives a new importance to distributed simulation. However, while existing techniquesexploit some levels of parallelism in the discrete-event simulation algorithm, they are usually targeted to specific applicat...
 
Editor's Note
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot
Issue Date:October 2000
pp. 1009-1012
No summary available.
 
Introducing the New Editor-in-Chief of the IEEE Transactions on Computers
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot
Issue Date:January 2003
pp. 1-2
No summary available.
 
Editor's Note
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot
Issue Date:July 2002
pp. 737-739
No summary available.
 
Editor's Note
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot
Issue Date:April 2001
pp. 289-291
No summary available.
 
Editor's Note
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot
Issue Date:May 2000
pp. 385-386
No summary available.
 
Editor's Note
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot
Issue Date:February 2000
pp. 97-99
No summary available.
 
Guest Editors' Introduction
Found in: IEEE Transactions on Computers
By Jean-Luc Gaudiot, Fabrizio Lombardi
Issue Date:June 1999
pp. 553-555
No summary available.
 
Packer: An innovative space-time-efficient parallel garbage collection algorithm based on virtual spaces
Found in: Parallel and Distributed Processing Symposium, International
By Shaoshan Liu, Ligang Wang, Xiao-Feng Li,Jean-Luc Gaudiot
Issue Date:May 2009
pp. 1-11
The fundamental challenge of garbage collector (GC) design is to maximize the recycled space with minimal time overhead. For efficient memory management, in many GC designs the heap is divided into large object space (LOS) and non-large object space (non-L...
 
Mark-Sharing: A Parallel Garbage Collection Algorithm for Low Synchronization Overhead
Found in: 2013 International Conference on Parallel and Distributed Systems (ICPADS)
By Hyunkyu Park,Changmin Lee,Seung Hun Kim,Won Woo Ro,Jean-Luc Gaudiot
Issue Date:December 2013
pp. 18-25
Two main problems prevent a parallel garbage collection (GC) scheme with lock-based synchronization from providing a high level of scalability: the load imbalance and the runtime overhead of thread synchronization operations. These problems become even mor...
 
Parallel Sparse Approximate Inverse Preconditioning on Graphic Processing Units
Found in: IEEE Transactions on Parallel and Distributed Systems
By Maryam Mehri Dehnavi,David M. Fernandez,Jean-Luc Gaudiot,Dennis D. Giannacopoulos
Issue Date:September 2013
pp. 1852-1862
Accelerating numerical algorithms for solving sparse linear systems on parallel architectures has attracted the attention of many researchers due to their applicability to many engineering and scientific problems. The solution of sparse systems often domin...
 
Acceleration of XML Parsing through Prefetching
Found in: IEEE Transactions on Computers
By Jie Tang,Shaoshan Liu,Chen Liu,Zhimin Gu,Jean-Luc Gaudiot
Issue Date:August 2013
pp. 1616-1628
Extensible Markup Language (XML) has become a widely adopted standard for data representation and exchange. However, its features also introduce significant overhead threatening the performance of modern applications. In this paper, we present a study of X...
 
Importance of Coherence Protocols with Network Applications on Multicore Processors
Found in: IEEE Transactions on Computers
By Kyueun Yi,Won W. Ro,Jean-Luc Gaudiot
Issue Date:January 2013
pp. 6-15
As Internet and information technology have continued developing, the necessity for fast packet processing in computer networks has also grown in importance. All emerging network applications require deep packet classification as well as security-related p...
 
Synchronization-Aware Energy Management for VFI-Based Multicore Real-Time Systems
Found in: IEEE Transactions on Computers
By Jian-Jun Han,Xiaodong Wu,Dakai Zhu,Hai Jin,Laurence T. Yang,Jean-Luc Gaudiot
Issue Date:December 2012
pp. 1682-1696
Voltage and frequency island (VFI) was recently adopted as an effective energy management technique for multicore processors. For a set of periodic real-time tasks that access shared resources running on a VFI-based multicore system with dynamic voltage an...
 
Packer: Parallel Garbage Collection Based on Virtual Spaces
Found in: IEEE Transactions on Computers
By Shaoshan Liu,Jie Tang,Ligang Wang,Xiao-Feng Li,Jean-Luc Gaudiot
Issue Date:November 2012
pp. 1611-1623
The fundamental challenge of garbage collector (GC) design is to maximize the recycled space with minimal time overhead. For efficient memory management, in many GC designs the heap is divided into large object space (LOS) and normal object space (non-LOS)...
 
Cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids
Found in: 2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)
By Changmin Lee,Won W. Ro,Jean-Luc Gaudiot
Issue Date:February 2012
pp. 33-40
This paper presents a cooperative heterogeneous computing framework which enables the efficient utilization of available computing resources of host CPU cores for CUDA kernels, which are designed to run only on GPU. The proposed system exploits at runtime ...
 
Keynote 3
Found in: 2011 IEEE 14th International Conference on Computational Science and Engineering (CSE 2011
By Jean-Luc Gaudiot
Issue Date:August 2011
pp. xxxi-xxxi
Summary form only given. The newly emerging many-core-on-a-chip designs have renewed an intense interest in parallel processing. By applying Amdahl's formulation to the programs in the PARSEC and SPLASH-2 benchmark suites, we find that most applications ma...
   
The Performance Analysis and Hardware Acceleration of Crypto-computations for Enhanced Security
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Jed Kao-Tung Chang, Shaoshan Liu, Jean-Luc Gaudiot, Chen Liu
Issue Date:December 2010
pp. 249-250
Security is very important in modern life due to most information is now stored in digital format. A good security mechanism will keep information secrecy and integrity, hence, plays an important role in modern information exchange. However, cryptography a...
 
Speculative Execution on GPU: An Exploratory Study
Found in: Parallel Processing, International Conference on
By Shaoshan Liu, Christine Eisenbeis, Jean-Luc Gaudiot
Issue Date:September 2010
pp. 453-461
We explore the possibility of using GPUs for speculative execution: we implement software value prediction techniques to accelerate programs with limited parallelism, and software speculation techniques to accelerate programs that contain runtime paralleli...
 
A Theoretical Framework for Value Prediction in Parallel Systems
Found in: Parallel Processing, International Conference on
By Shaoshan Liu, Christine Eisenbeis, Jean-Luc Gaudiot
Issue Date:September 2010
pp. 11-20
We present here a theoretical framework towards a fundamental understanding of the effects of value prediction. Our framework consists of two parts: first, an identification of the theoretical limit of value prediction and an indication of the potential to...
 
RHE: A Lightweight JVM Instructional Tool
Found in: Computer Software and Applications Conference, Annual International
By Shaoshan Liu, Chengrui Deng, Xiao-Feng Li, Jean-Luc Gaudiot
Issue Date:July 2009
pp. 612-619
Teaching Java Virtual Machine (JVM) has become essential in training the next generation of Web application engineers, embedded software engineers, as well as virtual machine researchers and practitioners. However, due to the lack of a suitable instruction...
 
Potential Impact of Value Prediction on Communication in Many-Core Architectures
Found in: IEEE Transactions on Computers
By Shaoshan Liu, Jean-Luc Gaudiot
Issue Date:June 2009
pp. 759-769
The newly emerging many-core-on-a-chip designs have renewed an intense interest in parallel processing. By applying Amdahl's formulation to the programs in the PARSEC and SPLASH-2 benchmark suites, we find that most applications may not have sufficient par...
 
An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation
Found in: IEEE Transactions on Computers
By Jung-Yup Kang, Sandeep K. Gupta, Jean-Luc Gaudiot
Issue Date:March 2008
pp. 375-388
In general, the main purpose for using PIM modules is to dramatically increase the Data-Level Parallelism (DLP) and avoid the limited issue rate of current systems (even when they include SIMD extensions) caused by the limited data bandwidth and functional...
 
Architectural Support for Network Applications on Simultaneous MultiThreading Processors
Found in: Parallel and Distributed Processing Symposium, International
By Kyueun Yi, Jean-Luc Gaudiot
Issue Date:March 2007
pp. 46
As network applications become increasingly sophisticated and internet traffic is getting heavier, future network processors must continue processing computation-intensive network applications at line rates. Most programmable network processors on the mark...
 
Design Trade-Offs and Deadlock Prevention in Transient Fault-Tolerant SMT Processors
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Xiaobin Li, Jean-Luc Gaudiot
Issue Date:December 2006
pp. 315-322
Since the very concept of Simultaneous Multi-Threading (SMT) entails inherent redundancy, some proposals have been made to run two copies of the same thread on top of SMT platforms in order to detect and correct soft errors. This allows, upon detection of ...
 
A Simple High-Speed Multiplier Design
Found in: IEEE Transactions on Computers
By Jung-Yup Kang, Jean-Luc Gaudiot
Issue Date:October 2006
pp. 1253-1258
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems, which depend on the execution of large numbers of multiplications. Previously reported algorithms mainly focused on rapidly reducing...
 
Features of Future Network Processor Architectures
Found in: John Vincent Atanasoff Modern Computing, International Symposium on
By Kyueun Yi, Jean-Luc Gaudiot
Issue Date:October 2006
pp. 69-76
As network applications are becoming increasingly sophisticated and internet traffic is getting heavier, future network processors must continue processing computation-intensive network applications at line rates. In this paper, we identify and describe in...
 
Throttling-Based Resource Management in High Performance Multithreaded Architectures
Found in: IEEE Transactions on Computers
By Seong-Won Lee, Jean-Luc Gaudiot
Issue Date:September 2006
pp. 1142-1152
Up to now, the power problems which could be caused by the huge amount of hardware resources present in modern systems have not been a primary concern. More recently, however, power consumption has begun limiting the number of resources which can be safely...
 
Foreword
Found in: IEEE Computer Architecture Letters
By Jean-Luc Gaudiot, Yale Patt, Kevin Skadon
Issue Date:January 2006
pp. N/A
Foreword for issue 1 of 2006
   
Area and System Clock Effects on SMT/CMP Throughput
Found in: IEEE Transactions on Computers
By James Burns, Jean-Luc Gaudiot
Issue Date:February 2005
pp. 141-152
Two approaches to high throughput processors are Chip Multi-Processing (CMP) and Simultaneous Multi-Threading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitionin...
 
Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture
Found in: Computational Systems Bioinformatics Conference, International IEEE Computer Society
By Jung-Yup Kang, Sandeep Gupta, Jean-Luc Gaudiot
Issue Date:August 2004
pp. 552-553
BLAST is a widely used tool to search for similarities in protein and DNA sequences. However, the kernels of BLAST are not efficiently supported by general-purpose processors because of the special computational requirements of the kernels.
   
A Fast and Well-Structured Multiplier
Found in: Digital Systems Design, Euromicro Symposium on
By Jung-Yup Kang, Jean-Luc Gaudiot
Issue Date:September 2004
pp. 508-515
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems which depend on extensive numbers of multiplications. Previously reported multiplication algorithms mainly focus on rapidly reducing ...
 
SPEAR: A Hybrid Model for Speculative Pre-Execution
Found in: Parallel and Distributed Processing Symposium, International
By Won W. Ro, Jean-Luc Gaudiot
Issue Date:April 2004
pp. 75b
<p>Speculative pre-execution achieves efficient data prefetching by running additional prefetching threads on spare hardware contexts. Various implementations for speculative pre-execution have been proposed, including compiler-based static approache...
 
An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Jung-Yup Kang, Sandeep Gupta, Saurabh Shah, Jean-Luc Gaudiot
Issue Date:June 2003
pp. 282
<p>Motion estimation is the most time consuming stage of MPEG family encodings and it has been shown to absorb up to 90% of the total execution time of MPEG processing. Therefore, we propose a hardware/software co-design paradigm that uses a PIM modu...
 
Dynamic Scheduling Issues in SMT Architectures
Found in: Parallel and Distributed Processing Symposium, International
By Chulho Shin, Seong-Won Lee, Jean-Luc Gaudiot
Issue Date:April 2003
pp. 77b
Simultaneous Multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughp...
 
HiDISC: A Decoupled Architecture for Data-Intensive Applications
Found in: Parallel and Distributed Processing Symposium, International
By Won W. Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain
Issue Date:April 2003
pp. 3b
<p>This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefe...
 
Compiler Support for Dynamic Speculative Pre-Execution
Found in: Interaction between Compilers and Computer Architecture, Annual Workshop on
By Won W. Ro, Jean-Luc Gaudiot
Issue Date:February 2003
pp. 14
Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), which contains the future probable cache miss instructions and backward slice, ca...
 
An Evaluation of Thread Migration for Exploiting Distributed Array Locality
Found in: High Performance Computing Systems and Applications, Annual International Symposium on
By Stephen Jenks, Jean-Luc Gaudiot
Issue Date:June 2002
pp. 190
<p>Thread migration is one approach to remote memory accesses on distributed memory parallel computers. In thread migration, threads of control migrate between processors to access data local to those processors, while conventional approaches tend to...
 
SMT Layout Overhead and Scalability
Found in: IEEE Transactions on Parallel and Distributed Systems
By James Burns, Jean-Luc Gaudiot
Issue Date:February 2002
pp. 142-155
<p><b>Abstract</b>—Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing microarchitectu...
 
MCOMA: A Multithreaded COMA Architecture
Found in: Computer Design, International Conference on
By Halima El Naga, Jean-Luc Gaudiot
Issue Date:September 2001
pp. 0523
Abstract: In this paper, we present a new Cache Only Memory Architecture, MCOMA, whose performance supersedes that of existing COMA architectures. This performance gain is obtained by basing the execution on multithreading principles and the provision of a...
 
Alias Analysis for Java with Reference-Set Representation
Found in: Parallel and Distributed Systems, International Conference on
By Jongwook Woo, Jean-Luc Gaudiot, Jehak Woo, Isabelle Attali, Denis Caromel, Andrew L Wendelborn
Issue Date:June 2001
pp. 0459
Abstract: We propose a flow-sensitive context-insensitive alias analysis in Java that is more efficient and precise than previous analyses in C++. For that, we propose a reference-set alias representation. Second, we present the propagation rules for the r...
 
Alias Analysis On Type Inference For Class Hierarchy In Java
Found in: Australasian Computer Science Conference
By Jongwook Woo, Jean-Luc Gaudiot, Isabelle Attali, Denis Caromel, Andrew L. Wendelborn
Issue Date:February 2001
pp. 206
The integration of alias analysis with type information increases the precision of alias detection, especially for inheritance among classes. This paper presents a compile-time flow-sensitive context-insensitive alias analysis algorithm with type informati...
 
An Over-partitioning Scheme for Parallel Sorting on Clusters with Processors Running at different Speeds
Found in: Cluster Computing, IEEE International Conference on
By Christophe Cérin, Jean-Luc Gaudiot
Issue Date:December 2000
pp. 385
No summary available.
   
Flow-Sensitive Alias Analysis with Referred-Set Representation for Java
Found in: High-Performance Computing in the Asia-Pacific Region, International Conference on
By Jongwook Woo, Jean-Luc Gaudiot, Jehak Woo
Issue Date:May 2000
pp. 485
Alias analysis refers to the determination of objects that may be accessed by two or more names. Many alias analysis algorithms have been proposed for several programming languages. In this paper, we propose a flow-sensitive alias analysis algorithm for Ja...
 
Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?
Found in: High-Performance Computer Architecture, International Symposium on
By James Burns, Jean-Luc Gaudiot
Issue Date:January 2000
pp. 109
Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing micro-architecture with relatively low overhead, thi...
 
Algorithms for Stable Sorting to Minimize Communications in Networks of Workstations and Their Implementations in BSP
Found in: Cluster Computing, International Workshop on
By Christophe Cérin, Jean-Luc Gaudiot
Issue Date:December 1999
pp. 112
In this paper we introduce our new approach to produce BSP (Bulk Synchronous Programming model) programs and we show their efficiency by implementing the stable sorting problem on clusters of PC. Experimental results on PCs based on Ethernet and Myrinet ca...
 
Communication Generation for Aligned and Cyclic(K) Distributions Using Integer Lattice
Found in: IEEE Transactions on Parallel and Distributed Systems
By Eric Hung-Yu Tseng, Jean-Luc Gaudiot
Issue Date:February 1999
pp. 136-146
<p><b>Abstract</b>—Optimizing communication is a key issue in generating efficient SPMD codes in compiling distributed arrays on data parallel languages, such as High Performance Fortran. In HPF, the array distribution may involve alignme...
 
Exploiting Global Data Locality in Non-Blocking Multithreaded Architectures
Found in: Parallel Architectures, Algorithms, and Networks, International Symposium on
By Wen-Yen Lin, Jean-Luc Gaudiot
Issue Date:December 1997
pp. 78
Non-Blocking Multithreaded architectures have been proposed as an effective means to overlap computation and communication in distributed memory systems. However, in these models, communication latency could only be hidden from computation as long as there...
 
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