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Displaying 1-20 out of 20 total
GASPARD — A Visual Parallel Programming Environment
Found in: Parallel Computing in Electrical Engineering, International Conference on
By Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet
Issue Date:September 2002
pp. 145
<p>In this paper, we present GASPARD (Graphical Array Specification for PARallel and Distributed computing) which is our visual programming environment devoted to the development of parallel applications.</p> <p>Task and data parallelism ...
 
Using Traceability to Enhance Mutation Analysis Dedicated to Model Transformation
Found in: Model-Driven Engineering, Verification, and Validation, Workshop on
By Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
Issue Date:October 2010
pp. 1-6
Techniques initially used for programs require modifications to be properly used with to model transformation characteristics. Mutation analysis is one of these techniques. IIt aims to qualify a test data set by analyzing the execution results of intention...
 
Visual Data-Parallel Programming for Signal Processing Applications
Found in: Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
By Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, Alain Demeure
Issue Date:February 2001
pp. 105
Matrix manipulation programs are easily developed using a visual language. For signal processing, a graph of tasks operates on arrays. Each task iterates the same code on different patterns tilling these arrays. In this case visual specifications of depend...
 
Master-Slave Control Structure for Massively Parallel System on Chip
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By Hana Krichene,Mouna Baklouti,Mohamed Abid,Philippe Marque,Jean-Luc Dekeyser
Issue Date:September 2013
pp. 917-924
The performance of massively parallel processing system depends mostly on the control configuration that is inherently part of the system. In particular, centralized control configuration is rigid and limits system scalability, and distributed control conf...
 
An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL
Found in: Computing in Science & Engineering
By A. Wendell O. Rodrigues,Frederic Guyomarc'h,Jean-Luc Dekeyser
Issue Date:January 2013
pp. 46-55
To reduce the design complexity of OpenCL programming, the approach proposed here generates application code automatically, based on model-driven engineering (MDE) and modeling and analysis of real-time and embedded (MARTE) systems. The aim is to provide a...
 
Hybrid system level power consumption estimation for FPGA-based MPSoC
Found in: Computer Design, International Conference on
By Santhosh Kumar Rethinagiri,Rabie Ben Atitallah,Smail Niar,Eric Senn,Jean-Luc Dekeyser
Issue Date:October 2011
pp. 239-246
This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for FPGA-based MPSoC. Within this methodology, the Functional Level Power Analysis (FLPA) is extended to set up generic power models for the different parts of the syst...
 
IP Based Configurable SIMD Massively Parallel SoC
Found in: International Conference on Field Programmable Logic and Applications
By Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean Luc Dekeyser
Issue Date:September 2010
pp. 247-250
Significant advances in the field of configurable computing have enabled parallel processing within a single Field-Programmable Gate Array (FPGA) chip. This paper presents the implementation of a flexible and programmable Single Instruction Multiple Data (...
 
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Jehangir Khan, Smail Niar, Atika Menhaj, Yassin Elhillali, Jean Luc Dekeyser
Issue Date:July 2008
pp. 126-131
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant systems, more precisely in collision avoidance and warning systems. An Automot...
 
A Graphical Framework for High Performance Computing Using An MDE Approach
Found in: Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
By Julien Taillard, Frédéric Guyomarc'h, Jean-Luc Dekeyser
Issue Date:February 2008
pp. 165-173
In this paper, we present a framework for Shared Memory Architectures that makes designing of parallel applications easier. We use the Model-Driven Engineering (MDE) approach and integrate new metamodels in Gaspard for each step of the design flow. The tar...
 
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Found in: Digital Systems Design, Euromicro Symposium on
By Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
Issue Date:September 2010
pp. 706-713
Reconfigurable FPGA based Systems-on-Chip (SoC)architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible nature. However due to the tremendous amount of hardware resources available in th...
 
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA
Found in: Computer Systems and Applications, ACS/IEEE International Conference on
By Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean Luc Dekeyser
Issue Date:May 2009
pp. 368-373
Single Instruction Multiple Data processors are increasingly used in embedded systems for multimedia applications because of their area and energy-efficiency. Neighboring communications between the processing elements are a key issue in SIMD processors. Th...
 
Using an MDE Approach for Modeling of Interconnection Networks
Found in: Parallel Architectures, Algorithms, and Networks, International Symposium on
By Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser
Issue Date:May 2008
pp. 289-294
As System-on-Chip (SoCs) become more complex, highperformance interconnection mediums are required to handle their complexity. Network-on-Chips (NoCs) enable integration of more Intellectual Properties (IPs) into theSoC with increased performance. In the r...
 
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
Found in: Real-Time Computing Systems and Applications, International Workshop on
By Rabie Ben Atitallah, Smail Niar, Samy Meftali, Jean-Luc Dekeyser
Issue Date:August 2007
pp. 525-533
To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) methods are needed to evaluate the different design alternatives. In this paper, we ...
 
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar
Found in: Digital Systems Design, Euromicro Symposium on
By Sebastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser
Issue Date:September 2006
pp. 280-287
The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are to be evaluated in practical doma...
 
A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks
Found in: Parallel and Distributed Processing Symposium, International
By Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M-Tahar Kechadi, Isaac D. Scherson
Issue Date:April 2003
pp. 277b
Interconnection network performance is a key factor when constructing parallel computers. The choice of an interconnection network used in a parallel computer depends on a large number of performance factors which are very often applications dependent. We ...
 
Parallelization of a 3D Magnetostatic Code Using High Performance Fortran
Found in: Parallel Computing in Electrical Engineering, International Conference on
By Emmanuel Cagniot, Jean Luc Dekeyser, Pierre Boulet, Thomas Brandes, Francis Piriou, Georges Marques
Issue Date:August 2000
pp. 181
Numerical simulation in electrical engineering allows reducing development costs by predicting device performance. An accurate prediction often requires 3D models, inducing high storage capacity and CPU power needs. As computation times can be very importa...
 
Modeling and Formal Validation of High-Performance Embedded Systems
Found in: Parallel and Distributed Computing, International Symposium on
By Abdoulaye Gamatié,Eric Rutten,Huafeng Yu,Pierre Boulet,Jean-Luc Dekeyser
Issue Date:July 2008
pp. 215-222
This paper presents an approach for the modeling and formalvalidation of high-performance systems. The approach relies on the repetitive model of computation used to express the parallelism of such systems within the Gaspard framework, which is dedicated t...
 
Master-Slave Control Structure for Massively Parallel System on Chip
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By Hana Krichene,Mouna Baklouti,Mohamed Abid,Philippe Marque,Jean-Luc Dekeyser
Issue Date:September 2013
pp. 917-924
The performance of massively parallel processing system depends mostly on the control configuration that is inherently part of the system. In particular, centralized control configuration is rigid and limits system scalability, and distributed control conf...
 
A Model-Driven Design Framework for Massively Parallel Embedded Systems
Found in: ACM Transactions on Embedded Computing Systems (TECS)
By Eric Piel, Abdoulaye Gamatie, Anne Etien, Jean-Luc Dekeyser, Philippe Marquet, Rabie Ben Atitallah, Sebastien Le Beux
Issue Date:November 2011
pp. 1-36
Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded systems specifical...
     
Scalable Multistage Network for Multiprocessor System-on-Chip Design
Found in: Parallel Architectures, Algorithms, and Networks, International Symposium on
By Sammy Meftali, Jean-luc Dekeyser, Isaac D. Scherson
Issue Date:December 2005
pp. 352-357
This paper presents a micro-network that is a generic, scalable and multi-stage interconnect architecture for systems on a chip (SoC). The network architecture relies on a packet switching and point-to-point bi-directional links between the routers impleme...
 
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