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Displaying 1-15 out of 15 total
Understanding the performance of concurrent error detecting superscalar microarchitectures
Found in: International Symposium on Signal Processing and Information Technology
By J.C. Smolens, Jangwoo Kim, J.C. Hoe, B. Falsafi
Issue Date:December 2005
pp. 13-18
Superscalar out-of-order micro architectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased ...
 
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James Hoe
Issue Date:December 2007
pp. 197-209
In deep sub-micron ICs, growing amounts of on- die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error ...
 
PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers
Found in: Pacific Rim International Symposium on Dependable Computing, IEEE
By Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe
Issue Date:December 2007
pp. 298-305
Several recent studies identify the memory system as the most frequent source of hardware failures in commercial servers. Techniques to protect the memory system from failures must continue to service memory requests, despite hardware failures. Furthermore...
 
TRUSS: A Reliable, Scalable Server Architecture
Found in: IEEE Micro
By Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk
Issue Date:November 2005
pp. 51-59
Traditional reliable servers require costly design changes to the processor, use custom system or application software, or cannot scale beyond a few processing elements. We present TRUSS, a family of server architectures providing reliable, scalable comput...
 
Store-Ordered Streaming of Shared Memory
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi
Issue Date:September 2005
pp. 75-86
<p>Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming provides a promising solution to the coherence miss bottleneck because i...
 
Temporal Streaming of Shared Memory
Found in: Computer Architecture, International Symposium on
By Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi
Issue Date:June 2005
pp. 222-233
<p>Coherent read misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. We propose Temporal Streaming, to eliminate coherent read misses by streaming data to...
 
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
Issue Date:December 2004
pp. 257-268
Previous proposals for soft-error tolerance have called for redundantly executing a program as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar design, the extra workload from redundant execution induces a severe perform...
 
Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth
Found in: IEEE Micro
By Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas G. Nowatzyk
Issue Date:November 2004
pp. 22-29
Fingerprinting summarizes the history of internal processor state updates into a cryptographic signature. The processors in a dual modular redundant pair periodically exchange and compare fingerprints to corroborate each other's correctness. relative to ot...
 
CMcloud: Cloud Platform for Cost-Effective Offloading of Mobile Applications
Found in: 2014 14th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid)
By Dongju Chae,Jihun Kim,Jangwoo Kim,Jong Kim,Seungjun Yang,Yeongpil Cho,Yongin Kwon,Yunheung Paek
Issue Date:May 2014
pp. 434-444
Recent efforts towards mobile cloud propose to offload mobile applications to cloud servers for the improved performance and battery life of mobile devices. However, existing schemes completely ignore the costs of cloud resources by assuming that idle serv...
 
ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming
Found in: IEEE Computer Architecture Letters
By Youngsok Kim,Jaewon Lee,Donggyu Kim,Jangwoo Kim
Issue Date:July 2013
pp. 1
Programmer-managed GPU memory is a major challenge in writing GPU applications. Programmers must rewrite and optimize an existing code for a different GPU memory size for both portability and performance. Alternatively, they can achieve only portability by...
 
GPUdmm: A high-performance and memory-oblivious GPU architecture using dynamic memory management
Found in: 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
By Youngsok Kim,Jaewon Lee,Jae-Eon Jo,Jangwoo Kim
Issue Date:February 2014
pp. 546-557
GPU programmers suffer from programmer-managed GPU memory because both performance and programmability heavily depend on GPU memory allocation and CPU-GPU data transfer mechanisms. To improve performance and programmability, programmers should be able to p...
   
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC
Found in: 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing (PRDC)
By Jangwoo Kim,Hyunggyun Yang,Mark P. Mccartney,Mudit Bhargava,Ken Mai,Babak Falsafi
Issue Date:December 2013
pp. 98-107
The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical role in the overall system performance, area, power, resilience, and yield. However, as process technologies scale down to nanometer-regime geometries, the design and i...
 
Guide-copy: fast and silent migration of virtual machine for datacenters
Found in: Proceedings of SC13: International Conference for High Performance Computing, Networking, Storage and Analysis (SC '13)
By Jangwoo Kim, Jihun Kim, Jong Kim, Dongju Chae
Issue Date:November 2013
pp. 1-12
Cloud infrastructure providers deploy Dynamic Resource Management (DRM) to minimize the cost of datacenter operation, while maintaining the Service Level Agreement (SLA). Such DRM schemes depend on the capability to migrate virtual machine (VM) images. How...
     
Fingerprinting: bounding soft-error detection latency and bandwidth
Found in: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems (ASPLOS-XI)
By Andreas G. Nowatzyk, Babak Falsafi, Brian T. Gold, James C. Hoe, Jangwoo Kim, Jared C. Smolens
Issue Date:October 2004
pp. 97-105
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a dual...
     
Memory coherence activity prediction in commercial workloads
Found in: Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture (WMPI '04)
By Anastassia Ailamaki, Babak Falsafi, Jangwoo Kim, Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch
Issue Date:June 2004
pp. 37-45
Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memory multiprocessors. Important commercial applications also show sensitivity to coherenc...
     
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