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Displaying 1-6 out of 6 total
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts
Found in: IEEE Micro
By James Coole,Greg Stitt
Issue Date:January 2014
pp. 42-53
High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies owing to orders-of-magnitude longer field-programmable gate array compilation times and limited support for changi...
 
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing
Found in: IEEE Design and Test of Computers
By Greg Stitt,Alan George,Herman Lam,Melissa Smith,Vikas Aggarwal,Gongyu Wang,James Coole,Casey Reardon,Brian Holland,Seth Koehler
Issue Date:July 2011
pp. 68-77
Editor's note:As part of their ongoing work with the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC), the authors are developing a complete tool chain for FPGA-based acceleration of scientific computing, from ...
 
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation
Found in: Reconfigurable Computing and FPGAs, International Conference on
By James Coole, John Wernsing, Greg Stitt
Issue Date:December 2009
pp. 143-148
Numerous studies have shown that field-programmable gate arrays (FPGAs) often achieve large speedups compared to microprocessors. However, one significant limitation of FPGAs that has prevented their use on important applications is the requirement for reg...
 
Fast and Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts
Found in: IEEE Micro
By James Coole,Greg Stitt
Issue Date:October 2013
pp. 1
High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies due to 1) orders-of- magnitude longer FPGA compilation times; and 2) limited support for changing or adding kernel...
 
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
Found in: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES/ISSS '10)
By Greg Stitt, James Coole
Issue Date:October 2010
pp. 13-22
Although hardware/software partitioning of embedded applications onto FPGAs is widely known to have performance and power advantages, FPGA usage has been typically limited to hardware experts, due largely to several problems: 1) difficulty of integrating h...
     
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures
Found in: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis (CODES/ISSS '08)
By Gaurav Chaudhari, Greg Stitt, James Coole
Issue Date:October 2008
pp. 1001-1001
Field-programmable gate arrays (FPGAs) often achieve order of magnitude speedups compared to microprocessors, but typically have been unable to improve the performance of applications with irregular memory access patterns, such as traversals of pointer-bas...
     
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