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Scaling to the End of Silicon with EDGE Architectures
By Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Mike Dahlin, Lizy K. John, Calvin Lin, Charles R. Moore, James Burrill, Robert G. McDonald, William Yoder, the TRIPS Team
Issue Date:July 2004
Post-RISC microprocessor designs must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, the TRIPS Team at the University of Texas ...
An evaluation of the TRIPS computer system
Found in: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (ASPLOS '09)
By Aaron Smith, Behnam Robatmili, Bertrand A. Maher, Doug Burger, James Burrill, Jeff Diamond, Katherine E. Coons, Kathryn S. McKinley, Mario Marino, Mark Gebhart, Nitya Ranganathan, Paul Gratz, Stephen W. Keckler
Issue Date:March 2009
The TRIPS system employs a new instruction set architecture (ISA) called Explicit Data Graph Execution (EDGE) that renegotiates the boundary between hardware and software to expose and exploit concurrency. EDGE ISAs use a block-atomic execution model in wh...
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