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Displaying 1-20 out of 20 total
Subspace Snooping: Exploiting Temporal Sharing Stability for Snoop Reduction
Found in: IEEE Transactions on Computers
By Jeongseob Ahn,Daehoon Kim,Jaehong Kim,Jaehyuk Huh
Issue Date:November 2012
pp. 1624-1637
Although snoop-based coherence protocols provide fast cache-to-cache transfers with a simple and robust coherence mechanism, scaling the protocols has been difficult due to the overheads of broadcast snooping. In this paper, we propose a coherence filterin...
 
Parameter-Aware I/O Management for Solid State Disks (SSDs)
Found in: IEEE Transactions on Computers
By Jaehong Kim, Sangwon Seo, Dawoon Jung, Jin-Soo Kim, Jaehyuk Huh
Issue Date:May 2012
pp. 636-649
Solid state disks (SSDs) have many advantages over hard disk drives, including better reliability, performance, durability, and power efficiency. However, the characteristics of SSDs are completely different from those of hard disk drives with rotating dis...
 
Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Junghoon Lee,Minjeong Shin,Hanjoon Kim,John Kim,Jaehyuk Huh
Issue Date:October 2011
pp. 177-178
The unique characteristics of prefetch traffic have not been considered in on-chip network design for multicore architectures. Most prefetchers are often oblivious to the network congestion when generating prefetech requests. In this work, we investigate t...
 
Secure MMU: Architectural support for memory isolation among virtual machines
Found in: Dependable Systems and Networks Workshops
By Seongwook Jin,Jaehyuk Huh
Issue Date:June 2011
pp. 217-222
In conventional virtualized systems, a hypervisor can access the memory pages of guest virtual machines without any restriction, as the hypervisor has a full control over the address translation mechanism. In this paper, we propose Secure MMU, a hardware-b...
 
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Daehoon Kim, Hwanju Kim, Jaehyuk Huh
Issue Date:December 2010
pp. 459-470
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such proliferation of virtualized systems opens a new opportunity to improve the scalab...
 
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger
Issue Date:November 2008
pp. 222-233
Data caches in general-purpose microprocessors often contain mostly dead blocks and are thus used inefficiently. To improve cache efficiency, dead blocks should be identified and evicted early. Prior schemes predict the death of a block immediately after i...
 
A NUCA Substrate for Flexible CMP Cache Sharing
Found in: IEEE Transactions on Parallel and Distributed Systems
By Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
Issue Date:August 2007
pp. 1028-1040
<p><b>Abstract</b>—We propose an organization for the on-chip memory system of a chip multiprocessor in which 16 processors share a 16-Mbyte pool of 64 level-2 (L2) cache banks. The L2 cache is organized as a nonuniform cache architecture...
 
Speculative Incoherent Cache Protocols
Found in: IEEE Micro
By Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi
Issue Date:November 2004
pp. 104-109
Coherence decoupling is a microarchitectural mechanism that implements separate protocols for speculative use and for the eventual verification of values. The technique reduces the effect of long communication latencies while mitigating the burdens on the ...
 
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
Found in: IEEE Micro
By Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles Moore
Issue Date:November 2003
pp. 46-51
<p>The TRIPS architecture seeks to deliver system-level configurability to applications and runtime systems. It does so by employing the concept of polymorphism, which permits the runtime system to configure the hardware execution resources to match ...
 
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
Found in: Computer Architecture, International Symposium on
By Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
Issue Date:June 2003
pp. 422
This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in...
 
Exploring the Design Space of Future CMPs
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Jaehyuk Huh, Doug Burger, Stephen W. Keckler
Issue Date:September 2001
pp. 0199
Abstract: In this paper, we study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the cores should h...
 
On-Chip Network Evaluation Framework
Found in: SC Conference
By Hanjoon Kim, Seulki Heo, Junghoon Lee, Jaehyuk Huh, John Kim
Issue Date:November 2010
pp. 10
With the number of cores on a chip continuing to increase, proper evaluation of on-chip network is critical for not only network performance but also overall system performance. In this paper, we show how a network-only simulation can be limited as it does...
 
Mutually Aware Prefetcher and On-Chip Network Designs for Multi-Cores
Found in: IEEE Transactions on Computers
By Junghoon Lee,Hanjoon Kim,Minjeong Shin,John Kim,Jaehyuk Huh
Issue Date:September 2014
pp. 2316-2329
Hardware prefetching has become an essential technique in high performance processors to hide long external memory latencies. In multi-core architectures with cores communicating through a shared on-chip network, traffic generated by the prefetchers can ac...
 
vCache: Providing a Transparent View of the LLC in Virtualized Environments
Found in: IEEE Computer Architecture Letters
By Daehoon Kim,Hwanju Kim,Jaehyuk Huh
Issue Date:July 2013
pp. 1
Since most of the current multi-core processors use a large last-level cache (LLC), efficient use of an LLC is critical for the overall performance of multi-cores. To improve the caching efficiency, page coloring is a representative software-based approach...
 
Revisiting hardware-assisted page walks for virtualized systems
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Jaehyuk Huh, Jeongseob Ahn, Seongwook Jin
Issue Date:June 2012
pp. 476-487
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current two-dimensional (2D) page walkers have been designed under the assumption that the usage patte...
     
Architectural support for secure virtualization under a vulnerable hypervisor
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Jaehyuk Huh, Jeongseob Ahn, Sanghoon Cha, Seongwook Jin
Issue Date:December 2011
pp. 272-283
Although cloud computing has emerged as a promising future computing model, security concerns due to malicious tenants have been deterring its fast adoption. In cloud computing, multiple tenants may share physical systems by using virtualization techniques...
     
Virtualizing performance asymmetric multi-core systems
Found in: Proceeding of the 38th annual international symposium on Computer architecture (ISCA '11)
By Changdae Kim, Jaehyuk Huh, Seungryoul Maeng, Youngjin Kwon
Issue Date:June 2011
pp. 45-56
Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric multi-core systems, operating systems are responsible for scheduling threads ...
     
Sector log: fine-grained storage management for solid state drives
Found in: Proceedings of the 2011 ACM Symposium on Applied Computing (SAC '11)
By Jaegeuk Kim, Jaehong Kim, Jaehyuk Huh, Seongwook Jin, Seungryoul Maeng
Issue Date:March 2011
pp. 360-367
Although NAND flash-based solid-state drives (SSDs) excel magnetic disks in several aspects, the costs of write operations have been limiting their performance. The overheads of write operations are exacerbated by the fixed write unit (page) of flash memor...
     
Subspace snooping: filtering snoops with operating system support
Found in: Proceedings of the 19th international conference on Parallel architectures and compilation techniques (PACT '10)
By Daehoon Kim, Jaehong Kim, Jaehyuk Huh, Jeongseob Ahn
Issue Date:September 2010
pp. 111-122
Although snoop-based coherence protocols provide fast cache-to-cache transfers with a simple and robust coherence mechanism, scaling the protocols has been difficult due to the overheads of broadcast snooping. In this paper, we propose a coherence filterin...
     
Coherence decoupling: making use of incoherence
Found in: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems (ASPLOS-XI)
By Doug Burger, Gurindar S. Sohi, Jaehyuk Huh, Jichuan Chang
Issue Date:October 2004
pp. 97-105
This paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol and a safe, backing coherence protocol. The SCL protocol produces a speculati...
     
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