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Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Neeraj Suri, Christof Fetzer, Jacob Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra
Issue Date:March 2008
pp. 1394-1395
No summary available.
   
Moore's Law and Beyond: Electronic Design Challenges
Found in: Electronic System Design, International Symposium on
By Jacob A. Abraham
Issue Date:December 2010
pp. 1
CMOS integrated circuit technology is expected to scale down for a few more technology nodes, enabling several billion transistors on a single chip. New technologies are now being explored as potential successors to CMOS. This talk will explore the challen...
 
Keynote Speech 1: New Paths for Test
Found in: Asian Test Symposium
By Jacob Abraham
Issue Date:October 2007
pp. 3
Test techniques for screening defective integrated circuits (ICs) after manufacture have to consider potential defects as well as the cost. In the future, test must deal with trends including advances in IC technology which continue to reduce feature sizes...
   
Small-Delay Defect Detection in the Presence of Process Variations
Found in: Quality Electronic Design, International Symposium on
By Rajeshwary Tayade, Savithri Sundereswaran, Jacob Abraham
Issue Date:March 2007
pp. 711-716
Interconnect based defects such as resistive via are be- coming more prevalent in nanoscale designs. Such defects can be classified as latent defects that affect circuit reliabil- ity and are generally modeled as small-delay defects. One method to detect t...
 
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs
Found in: VLSI Design, International Conference on
By Jacob A. Abraham, Daniel G. Saab
Issue Date:January 2007
pp. 6
<p>Integrated circuit technology has evolved from micro-controllers and discrete components to fully integrating a large system on a single chip (SoC). Today, verification is the most expensive component in the design cycle in term of cost and time. ...
   
Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction
Found in: 2013 22nd Asian Test Symposium (ATS)
By Hsun-Cheng Lee,Jacob A. Abraham
Issue Date:November 2013
pp. 128-133
Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay line ADCs are ha...
 
Special session 12B: Panel post-silicon validation & test in huge variance era
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Takahiro J. Yamaguchi,Jacob A. Abraham,Gordon W. Roberts,Suriyaprakash Natarajan,Dennis Ciplickas
Issue Date:April 2013
pp. 1
At the 1999 ITC, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. At t...
 
Enhanced algorithm of combining trace and scan signals in post-silicon validation
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Kihyuk Han,Joon-Sung Yang,Jacob A. Abraham
Issue Date:April 2013
pp. 1-6
As the complexity of integrated circuit design increases and production schedules become shorter, the dependency on post-silicon validation for capturing design errors that escape from pre-silicon verification also increases. A major challenge in post-sili...
 
A framework for low overhead hardware based runtime control flow error detection and recovery
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Ameya Chaudhari,Junyoung Park,Jacob Abraham
Issue Date:April 2013
pp. 1-6
Transient errors during execution of a process running on a processor can lead to serious system failures or security lapses. It is necessary to detect, and if possible, correct these errors before any damage is caused to the system. Of the many approaches...
 
Dynamic Trace Signal Selection for Post-Silicon Validation
Found in: 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems
By Kihyuk Han,Joon-Sung Yang,Jacob A. Abraham
Issue Date:January 2013
pp. 302-307
In order to gain market share in today's competitive high-tech industry, fast time-to-market (TTM) is one of the key factors for the success of a product. Since pre-silicon verification cannot be applied exhaustively as the size and complexity of the integ...
 
FALCON: Rapid statistical fault coverage estimation for complex designs
Found in: 2012 IEEE International Test Conference (ITC)
By Shahrzad Mirkhani,Jacob A. Abraham,Toai Vo,Hongshin Jun,Bill Eklow
Issue Date:November 2012
pp. 1-10
FALCON (FAst fauLt COverage estimatioN) is a scalable method for fault grading which uses local fault simulations to estimate the fault coverage of a large system. The generality of this method makes it applicable for any modular design. Our analysis shows...
 
Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By Ameya Chaudhari,Jacob Abraham
Issue Date:June 2012
pp. 162-167
Hardware based execution monitoring of applications holds the promise for an effective and tamper-proof solution for intrusion detection on processor. This paper presents a practical hardware based intrusion detection framework which uses stream cipher bas...
 
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management
Found in: VLSI Design, International Conference on
By Junyoung Park,H. Mert Ustun,Jacob A. Abraham
Issue Date:January 2012
pp. 155-160
Due to the increasing trend toward greater processor power density and computationally intensive applications, Dynamic Thermal Management (DTM) has become an essential technique in modern processors. Among many DTM techniques, Dynamic Voltage Scaling (DVS)...
 
On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test
Found in: Asian Test Symposium
By Hyunjin Kim,Jacob A. Abraham
Issue Date:November 2011
pp. 15-20
Memory interface speed has been rapidly increasing to overcome the performance gaps between microprocessor and memory. Testing the I/O timing parameters at-speed has become a challenge because of the limitations on the test clock frequencies provided by lo...
 
Post-Silicon Timing Validation Method Using Path Delay Measurements
Found in: Asian Test Symposium
By Eun Jung Jang,Jaeyong Chung,Anne Gattiker,Sani Nassif,Jacob A. Abraham
Issue Date:November 2011
pp. 232-237
In the nanometer era, the mismatch between the pre-silicon model and the post-silicon timing behavior is becoming severer. Therefore, it is necessary to validate timing with post-silicon data. We propose a method that estimates all the segment delays in th...
 
CEDA: Control-Flow Error Detection Using Assertions
Found in: IEEE Transactions on Computers
By Ramtilak Vemu,Jacob A. Abraham
Issue Date:September 2011
pp. 1233-1245
This paper presents an efficient software technique, control-flow error detection through assertions (CEDA), for online detection of control-flow errors. Extra instructions are automatically embedded into the program at compile time to continuously update ...
 
Arbitrary Waveform Generator Response Shaping Method to Enable ADC Linearity Testing on Very Low Cost Automatic Test Equipment
Found in: Mixed-Signals, Sensors, and Systems Test Workshop, IEEE 14th International
By Sachin Dileep Dasnurkar,Jacob A. Abraham
Issue Date:May 2011
pp. 67-71
Mixed signal parametric testing is resource intensive and requires high-precision source and capture instrumentation to screen parametric faults. Analog to digital converters (ADC) require analog sources to provide stimulus while digital instrumentation wi...
 
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces
Found in: Asian Test Symposium
By Hyunjin Kim, Jacob A. Abraham
Issue Date:December 2010
pp. 123-128
A built-in self-test (BIST) for testing high speed source-synchronous memory interfaces has been designed using 0.18-um TSMC process. To overcome limitations of the resolution and the accuracy in low-cost automated test equipment (ATE), a cycle-by-cycle co...
 
At-speed Test of High-Speed DUT Using Built-Off Test Interface
Found in: Asian Test Symposium
By Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh
Issue Date:December 2010
pp. 269-274
This paper presents an efficient test framework to extend a use of low-cost ATE (Automatic Test Equipment) to at-speed test of high-speed DUT (Device Under Test). To bridge the speed gap between the ATE and the DUT, an off-chip test interface circuit, call...
 
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham
Issue Date:October 2009
pp. 136-144
This paper presents a SNR-aware error detection technique for a low-power wavelet lifting transform architecture in JPEG 2000. Power reduction is done by over-scaling the supply voltage (voltage-over-scaling (VOS)). A low-cost SNR-aware detection logic is ...
 
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
Found in: On-Line Testing Symposium, IEEE International
By Abhijit Chatterjee, Jacob Abraham, Adit Singh, Elie Maricau, Rakesh Kumar, Christos Papachristou
Issue Date:June 2009
pp. 129
There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that erro...
 
Error detection in 2-D Discrete Wavelet lifting transforms
Found in: On-Line Testing Symposium, IEEE International
By Shih-Hsin Hu, Jacob A. Abraham
Issue Date:June 2009
pp. 170-175
Discrete Wavelet transform is a powerful mathematics technique which is being adopted in different applications including physics, image processing, biomedical signal processing, and communication. Due to its pipelined structure and multirate processing re...
 
Vector based Analog to Digital Converter sequential testing methodology to minimize ATE memory and analysis requirements
Found in: Mixed-Signals, Sensors, and Systems Test Workshop, IEEE 14th International
By Sachin Dileep Dasnurkar, Jacob A. Abraham
Issue Date:June 2009
pp. 1-5
Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external...
 
Closed-loop Built in Self Test for PLL production testing with minimal tester resources
Found in: Mixed-Signals, Sensors, and Systems Test Workshop, IEEE 14th International
By Sachin Dasnurkar, Jacob Abraham
Issue Date:June 2009
pp. 1-5
Phase Locked Loops (PLLs) are extensively used in modern System on a Chip (SoC) modules for generating timing, clock signal recovery and to provide a timing reference for communication interfaces. Due to their use in crucial and omnipresent applications, P...
 
Critical Path Selection for Delay Test Considering Coupling Noise
Found in: European Test Symposium, IEEE
By Rajeshwary Tayade, Jacob A. Abraham
Issue Date:May 2009
pp. 163-168
Identifying the set of real critical paths of a circuit is an important step in delay testing. Since path delays are
 
On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector
Found in: VLSI Test Symposium, IEEE
By Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
Issue Date:May 2009
pp. 285-290
This paper develops a technique, using a built-in detector, for measuring the specifications of RF subsystems and fine-tuning them with a feedback control algorithm. At the same time, optimum power consumption points can be chosen from different biasing sc...
 
Recursive Path Selection for Delay Fault Testing
Found in: VLSI Test Symposium, IEEE
By Jaeyong Chung, Jacob A. Abraham
Issue Date:May 2009
pp. 65-70
This paper presents a new path selection algorithm for delay fault testing in a statistical timing framework. Existing algorithms which consider correlation between paths use an iterative process for each path or defect and require a Monte Carlo simulation...
 
Characterization of sequential cells for constraint sensitivities
Found in: Quality Electronic Design, International Symposium on
By Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal
Issue Date:March 2009
pp. 74-79
For timing analysis, each flip-flop and latch in a standard library is characterized for two constraints: setup time and hold time constraints. These constraints need to be characterized for their sensitivities to the variation parameters in order to perfo...
 
Functionally valid gate-level peak power estimation for processors
Found in: Quality Electronic Design, International Symposium on
By Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham
Issue Date:March 2009
pp. 753-758
Traditionally, peak power consumption has been estimated at the module-level and there has been no attempt to check the functional validity of the gate-level estimate through instruction execution. This leads to the overdesign of the processor components t...
 
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL
Found in: VLSI Design, International Conference on
By Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
Issue Date:January 2009
pp. 77-82
We present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level (RTL). We guarantee the correctness of any low power transformation by provid...
 
Budget-Dependent Control-Flow Error Detection
Found in: On-Line Testing Symposium, IEEE International
By Ramtilak Vemu, Jacob A. Abraham
Issue Date:July 2008
pp. 73-78
The problem of detection of control flow errors in software has been studied extensively in literature and many detection techniques have been proposed. These techniques typically have high memory and performance overheads and hence are unusable for real-t...
 
Characterization and testing of microelectromechnical accelerometers
Found in: Mixed-Signals, Sensors, and Systems Test Workshop, IEEE 14th International
By Sachin Dasnurkar, Jacob Abraham
Issue Date:June 2008
pp. 1-6
Analog and Mixed Signal circuits pose a greater challenge in semiconductor testing than digital circuits due to the complexity of test requirements and the extremely large test vector sample space [?]. MicroElectroMechanical Systems (MEMS) are an emerging ...
 
Jitter Decomposition in High-Speed Communication Systems
Found in: European Test Symposium, IEEE
By Qingqi Dou, Jacob A. Abraham
Issue Date:May 2008
pp. 157-162
Jitter impairs the bit-error rate in high-speed communication systems. Jitter decomposition is important for accurately deriving the total jitter in a system and for aiding in identifying the root causes of jitter. We extend a previous approach for jitter ...
 
Critical Path Selection for Delay Test Considering Coupling Noise
Found in: European Test Symposium, IEEE
By Rajeshwary Tayade, Jacob A. Abraham
Issue Date:May 2008
pp. 119-124
Identifying the set of real critical paths of a circuit is an important step in delay testing. Since path delays are vector dependent, the set of critical paths selected dependson the vectors assumed when estimating the path delays. To find the real critic...
 
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Xiao Pu, Axel Thomsen, Jacob Abraham
Issue Date:April 2008
pp. 168-172
The loop bandwidth of fractional-N PLL is a desirable parameter for many wireless communication applications. To improve bandwidth design tradeoffs must be made among different circuit blocks. The key to successful implementation of a wideband fractional-N...
 
Parallel Loopback Test of Mixed-Signal Circuits
Found in: VLSI Test Symposium, IEEE
By Joonsung Park, Hongjoong Shin, Jacob A. Abraham
Issue Date:May 2008
pp. 309-316
Parallel testing of mixed-signal circuits has been considered a difficult task due to the limited resources in generating and analyzing multiple analog signals. A number of methods have been proposed to perform parallel testing of mixed-signal circuits usi...
 
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems
Found in: VLSI Test Symposium, IEEE
By Qingqi Dou, Jacob A. Abraham
Issue Date:May 2008
pp. 3-8
Time Interleaved A/D Converters (TIADCs)provide an attractive solution to the realization of analogfront ends in high speed communication systems. However,gain mismatch, offset mismatch, and sampling time mismatchbetween time-interleaved channels limit the...
 
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors
Found in: VLSI Test Symposium, IEEE
By Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
Issue Date:May 2008
pp. 203-208
This paper describes the theory and chip measurements of a built-in test technique for RF receivers which uses simple RF amplitude detectors. The method has been used to measure the performance parameters of a 940 MHz RF receiver front-end with a mixer and...
 
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits
Found in: VLSI Test Symposium, IEEE
By Byoungho Kim, Nash Khouzam, Jacob A. Abraham
Issue Date:May 2008
pp. 293-298
Accurate measurement of sub-picosecond aperture jitter when testing state-of-the-art high-speed, high-resolution data converters is a difficult problem, since there is no systematic method of precisely separating aperture jitter from input and clock jitter...
 
Implications of Technology Trends on System Dependability
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Jacob A. Abraham
Issue Date:March 2008
pp. 940
No summary available.
 
A low-cost concurrent error detection technique for processor control logic
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
Issue Date:March 2008
pp. 897-902
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transient faults, the technique selects faults which have a high probability of caus...
 
Characterization of Standard Cells for Intra-Cell Mismatch Variations
Found in: Quality Electronic Design, International Symposium on
By Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
Issue Date:March 2008
pp. 213-219
With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variations (referred to as, statistical characterization). Statistical characterization need to be performed efficiently...
 
Cache Design for Low Power and High Yield
Found in: Quality Electronic Design, International Symposium on
By Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob Abraham
Issue Date:March 2008
pp. 103-107
A novel circuit approach to increase SRAM Static Noise Margin (SNM) and enable lower operating voltage is described. Increasing process variability for new technologies coupled with increased reliability effects like Negative Bias Temperature Instability (...
 
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
Found in: VLSI Design, International Conference on
By Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
Issue Date:January 2008
pp. 521-526
We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power...
 
Test Education in the Global Economy
Found in: Asian Test Symposium
By Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu
Issue Date:October 2007
pp. 53
There is an increasing demand for test and diagnosis expertise in the global semiconductor industry, in sectors ranging from foundries to test houses, to IDM companies, and from fabless design houses to EDA companies. Test education, however remains a nich...
   
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems
Found in: IEEE Transactions on Computers
By Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham
Issue Date:October 2007
pp. 1401-1414
This paper presents a novel technique for proving the correctness of arithmetic circuit designs described at the Register Transfer Level (RTL). The technique begins with the automatic translation of circuits from a Verilog RTL description into a Term Rewri...
 
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
Found in: European Test Symposium, IEEE
By Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab
Issue Date:May 2007
pp. 173-178
We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback ...
 
Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications
Found in: VLSI Test Symposium, IEEE
By Byoungho Kim, Zhenhai Fu, Jacob A. Abraham
Issue Date:May 2007
pp. 291-296
Loopback tests for a differential mixed-signal Device Under Test (DUT) have rarely been attempted, since any imbalance introduced by a Design for Test (DfT) circuitry on differential signaling delivers an imperfect sinusoidal wave to the DUT input, thereby...
 
Built-In Test of RF Mixers Using RF Amplitude Detectors
Found in: Quality Electronic Design, International Symposium on
By Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
Issue Date:March 2007
pp. 404-409
This paper describes a low cost, high resolution, built-in test technique for RF mixers which uses a simple RF amplitude detector. The method has been used to predict the performance parameters of a 940 MHz RF mixer. The detector has small area overhead wi...
 
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model
Found in: Quality Electronic Design, International Symposium on
By Joonsung Park, Hongjoong Shin, Jacob A. Abraham
Issue Date:March 2007
pp. 495-500
Pseudorandom test of analog and mixed-signal circuits provides a low-cost test solution, however, its application has been restricted to linear circuit testing. This paper presents an efficient pseudorandom test method for nonlinear circuits. Our method us...
 
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