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Displaying 1-24 out of 24 total
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
Found in: VLSI Test Symposium, IEEE
By M.B. Santos, F.M. Gongalves, I.C. Teixeira, J.P. Teixeira
Issue Date:April 1999
pp. 326
No summary available.
 
Quality of Electronic Design: From Architectural Level to Test Coverage
Found in: Quality Electronic Design, International Symposium on
By O.P. Dias, J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:March 2000
pp. 197
The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, e...
 
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes
Found in: On-Line Testing Symposium, IEEE International
By M. Rodríguez-Irago, J.J. Rodríguez Andina, F. Vargas, J. Semião, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2006
pp. 257-262
Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs...
 
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By F.M. Goncalves, I.C. Teixeira, J.P. Teixeira
Issue Date:October 1997
pp. 29
The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, b...
 
Test preparation for high coverage of physical defects in CMOS digital ICs
Found in: VLSI Test Symposium, IEEE
By M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Issue Date:May 1995
pp. 0330
Abstract: In this paper, a novel methodology for test preparation of digital ICs, aiming at high defect coverage and affordable computational effort, is proposed. A method is presented to heuristically generate a list of pseudo realistic (PSE) faults, at g...
 
From System Level to Defect-Oriented Test: A Case Study
Found in: European Test Workshop, IEEE
By J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:September 1999
pp. 136
The purpose of this paper is to demonstrate the usefulness of a recently proposed Object-Oriented (OO) based methodology and tools (SysObj and Test-Adder) when applied in the design of testable hardware modules (eventually used as embedded cores in SOCs). ...
 
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By F.M. Goncalves, I.C. Teixeira, J.P. Teixeira
Issue Date:November 1996
pp. 96
No summary available.
 
Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits
Found in: European Design and Test Conference
By C. Sebeke, J.P. Teixeira, M.J. Ohletz
Issue Date:March 1995
pp. 464
A comprehensive tool has been implemented for the comparison of different test preparation techniques and target faults. It comprises of the realistic fault characterisation program LIFT that can extract sets of various faults from a given analogue or mixe...
 
Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test
Found in: 11th IEEE International On-Line Testing Symposium
By M. Rodriguez-Irago,J.J. Rodriguez Andina,F. Vargas,M.B. Santos,I.C. Teixeira,J.P. Teixeira
Issue Date:May 2014
pp. 281,282,283,284,285,286
Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-V/sub DD/ test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulat...
 
Test Resource Partitioning: A Design and Test Issue
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J.P. Teixeira, I.M. Teixeira, O.P. Dias, J. Semião, C.E. Pereira
Issue Date:March 2001
pp. 0034
Abstract: Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis ...
   
MOSYS A Methodology for Automatic Object Identification from System Specification
Found in: Object-Oriented Real-Time Distributed Computing, IEEE International Symposium on
By L.B. Becker, C.E. Pereira, O.P. Dias, I.M. Teixeira, J.P. Teixeira
Issue Date:March 2000
pp. 198
This paper presents a new approach to the automatic identification of objects/classes from a system specification. The methodology is aimed at the development of Distributed Real-Time Systems (DRTS), specially those conceived for industrial automation appl...
 
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs
Found in: International Conference on Field Programmable Logic and Applications
By V. Bexiga,C. Leong,J. Semião,I.C. Teixeira,J.P. Teixeira,M. Valdés,J. Freijedo,J.J. Rodríguez-Andina,F. Vargas
Issue Date:September 2011
pp. 301-304
The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval...
 
Built-in aging monitoring for safety-critical applications
Found in: On-Line Testing Symposium, IEEE International
By J.C. Vazquez, V. Champac, A.M. Ziesemer, R. Reis, I.C. Teixeira, M.B. Santos, J.P. Teixeira
Issue Date:June 2009
pp. 9-14
Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasi...
 
Design and test methodology for a reconfigurable PEM data acquisition electronics system
Found in: International Conference on Field Programmable Logic and Applications
By C. Leong, P. Bento, J.P. Teixeira, I.C. Teixeira, P. Rodrigues, A. Trindade, J.C. Silva, J. Varela, J. Rego, J. Nobre, P. Lousa
Issue Date:August 2005
pp. 523-526
The purpose of this paper is to present the main aspects of a design and test (D&T) methodology used in the development of a specific type of system. The application focuses medical imaging using a compact positron emission mammography (PEM) detector w...
 
Hardware/Software Specification, Design and Test using a System Level Approach
Found in: Integrated Circuit Design and System Design, Symposium on
By O.P. Dias, J. Semião, C.E. Pereira, I.M. Teixeira, J.P. Teixeira
Issue Date:October 1999
pp. 0042
The purpose of this paper is to present an environment that allows the reliable, in-time system specification and design of complex hardware/software (hw/sw) systems. The Object Oriented (OO) paradigm underlies models, methodologies, languages and tools. T...
 
HW/SW specification using OOM techniques
Found in: Rapid System Prototyping, IEEE International Workshop on
By M. Calha, J.P. Teixeira, I.C. Teixeira
Issue Date:June 1996
pp. 96
The ever increasing complexity and networking of hardware/software (hw/sw) systems, together with tough competitiveness and shrinking time-to-market puts a heavy burden on system design methodologies. For rapid system prototyping, design productivity is ma...
 
Test preparation methodology for high coverage of physical defects in CMOS digital ICs
Found in: European Design and Test Conference
By M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Issue Date:March 1995
pp. 604
The constant increase of IC circuit complexity and quality requirements make high quality testing a difficult challenge. In this work, a methodology for test preparation leading to high physical defect coverage is proposed. Two new software tools are prese...
   
Teaching Microelectronic-Based Integrated Systems Design and Test
Found in: Microelectronics Systems Education, IEEE International Conference on/Multimedia Software Engineering, International Symposium on
By F.M. Goncalves, J.P. Teixeira
Issue Date:July 1999
pp. 65
No summary available.
 
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By J. Semião, J. Freijedo, J.J. Rodríguez-Andina, F. Vargas, M.B. Santos, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2007
pp. 167-172
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (VDD) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional ...
 
Design and test issues of a FPGA based data acquisition system for medical imaging using PEM
Found in: IEEE-NPSS Real Time Conference
By C. Leong, P. Bento, P. Rodrigues, J.C. Silva, A. Trindade, P. Lousa, J. Rego, J. Nobre, J. Varela, J.P. Teixeira, C. Teixeira
Issue Date:June 2005
pp. 92
The main aspects of the design and test (D&T) of a reconfigurable architecture for the data acquisition electronics (DAE) system of the clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (positro...
 
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST
Found in: Test Conference, International
By M.B. Santos, I.C. Teixeira, J.P. Teixeira, S. Manich, R. Rodriquez, J. Figueras
Issue Date:October 2002
pp. 814
While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudo-random based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste ...
 
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Found in: European Test Workshop, IEEE
By M.B. Santos, F.M. Gonçalves, I.C. Teixeira, J.P. Teixeira
Issue Date:June 2001
pp. 99
The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability M...
 
Controllability and observability in mixed signal cores
Found in: On-Line Testing Symposium, IEEE International
By Jose Rocha, Nuno Dias, Angelo Monteiro, Alexandre Neves, Gabriel Santos, Marcelino Santos, J.P. Teixeira
Issue Date:June 2009
pp. 198-200
Observability is mandatory for debugging purposes in all microelectronic systems. Mixed signal cores, in particular, require high observability in order to allow post production debug and to drive the design enhancements towards the real non-ideal behaviou...
 
13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems
Found in: VLSI Test Symposium, IEEE
By F.M. Gonçalves, J.P. Teixeira
Issue Date:April 1998
pp. 283
No summary available.
 
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