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Displaying 1-19 out of 19 total
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. Freijedo, J. J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:April 2007
pp. 1-6
As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology t...
 
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Semião, J. J. Rodríguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:September 2007
pp. 303-311
A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. In the prop...
 
The influence of clock-gating on NBTI-induced delay degradation
Found in: 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
By J. Pachito,C. V. Martins,J. Semiao,M. Santos,I. C. Teixeira,J. P. Teixeira
Issue Date:June 2012
pp. 61-66
This paper presents an analysis of the implications of clock gating techniques on the increase of aging degradations in new node digital circuits. NBTI is the dominant effect that cause long-term performance degradations over time, and circuit operating co...
 
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects
Found in: Latin American Test Workshop
By M. Valdes,J. Freijedo,M. J. Moure,J. J. Rodriguez-Andina,J. Semiao,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-7
In current nanometer technologies, aging effects (due for instance to Negative Bias Thermal Instability) may appear after relatively short operating times, compared to the expected lifetime of circuits, even for relatively short-cycle consumer electronics....
 
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies
Found in: On-Line Testing Symposium, IEEE International
By J. Semiao, J. Freijedo, J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:June 2009
pp. 223-228
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-fau...
 
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By J. Semião, J. Freijedo, J.J. Rodríguez-Andina, F. Vargas, M.B. Santos, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2007
pp. 167-172
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (VDD) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional ...
 
Modeling the effect of process variations on the timing response of nanometer digital circuits
Found in: Latin American Test Workshop
By J. Freijedo,J. Semiao,J. J. Rodriguez-Andina,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-5
The implementation of complex, high-performance functionality in nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This p...
 
Predictive error detection by on-line aging monitoring
Found in: On-Line Testing Symposium, IEEE International
By J. C. Vazquez, V. Champac, A. M. Ziesemer, R. Reis, J. Semiao, I. C. Teixeira, M. B. Santos, J. P. Teixeira
Issue Date:July 2010
pp. 9-14
The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or ...
 
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:April 2008
pp. 1-4
This paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to V<inf>DD</inf> and temperature (T) instability, even in the presence of process var...
 
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits
Found in: VLSI, IEEE Computer Society Annual Symposium on
By J. Semiao, J. Freijedo, J.J. Rodríguez Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:March 2007
pp. 207-212
As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, we propose a new methodology to enhance circuit tolerance to powersupply voltage (VDD) local variations, without degrading its perfo...
 
Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage
Found in: Design and Diagnostics of Electronic Circuits and Systems
By F. Guerreiro, J. Semiao, A. Pierce, M.B. Santos, I.M. Teixeira
Issue Date:April 2006
pp. 277-282
No summary available.
 
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs
Found in: International Conference on Field Programmable Logic and Applications
By V. Bexiga,C. Leong,J. Semião,I.C. Teixeira,J.P. Teixeira,M. Valdés,J. Freijedo,J.J. Rodríguez-Andina,F. Vargas
Issue Date:September 2011
pp. 301-304
The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval...
 
Investigating the Use of BICS to detect resistive-open defects in SRAMs
Found in: On-Line Testing Symposium, IEEE International
By R. Chipana, L. Bolzani, F. Vargas, J. Semiao, J. Rodriguez-Andina, I. Teixeira, P. Teixeira
Issue Date:July 2010
pp. 200-201
Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused ...
 
Hardware/Software Specification, Design and Test using a System Level Approach
Found in: Integrated Circuit Design and System Design, Symposium on
By O.P. Dias, J. Semião, C.E. Pereira, I.M. Teixeira, J.P. Teixeira
Issue Date:October 1999
pp. 0042
The purpose of this paper is to present an environment that allows the reliable, in-time system specification and design of complex hardware/software (hw/sw) systems. The Object Oriented (OO) paradigm underlies models, methodologies, languages and tools. T...
 
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes
Found in: On-Line Testing Symposium, IEEE International
By M. Rodríguez-Irago, J.J. Rodríguez Andina, F. Vargas, J. Semião, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2006
pp. 257-262
Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs...
 
Quality of Electronic Design: From Architectural Level to Test Coverage
Found in: Quality Electronic Design, International Symposium on
By O.P. Dias, J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:March 2000
pp. 197
The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, e...
 
On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications
Found in: Latin American Test Workshop
By R. S. Oliveira,J. Semiao,I. C. Teixeira,M. B. Santos,J. P. Teixeira
Issue Date:March 2011
pp. 1-6
Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging process. Such variations induce abnormal timing delays leading to systems er...
 
Test Resource Partitioning: A Design and Test Issue
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J.P. Teixeira, I.M. Teixeira, O.P. Dias, J. Semião, C.E. Pereira
Issue Date:March 2001
pp. 0034
Abstract: Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis ...
   
From System Level to Defect-Oriented Test: A Case Study
Found in: European Test Workshop, IEEE
By J. Semião, M.B. Santos, I.M. Teixeira, J.P. Teixeira
Issue Date:September 1999
pp. 136
The purpose of this paper is to demonstrate the usefulness of a recently proposed Object-Oriented (OO) based methodology and tools (SysObj and Test-Adder) when applied in the design of testable hardware modules (eventually used as embedded cores in SOCs). ...
 
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