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Displaying 1-27 out of 27 total
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs
Found in: Test Conference, International
By B. Alorda, M. Rosales, J. Soden, C. Hawkins, J. Segura
Issue Date:October 2002
pp. 947
We analyze a transient current testing technique that measures and computes the charge delivered to the circuit during the transient operation. The method was applied to 0.5 ?m CMOS SRAMs that passed various logic tests. Results indicate that Charge Based ...
 
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing
Found in: Test Conference, International
By B. Alorda, B. Bloechel, A. Keshavarzi, J. Segura
Issue Date:October 2003
pp. 719
We present a measurement module that computes the charge from the transient supply current and provides a digital value of this magnitude. The module is constructed to provide a feasible implementation of transient current testing in production-like enviro...
 
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor
Found in: On-Line Testing Workshop, IEEE International
By B. Alorda, I. de Paul, J. Segura, T. Miller
Issue Date:July 2000
pp. 87
This work presents a prototype architecture that provides on-line IDDQ measurement for a microprocessor based on system. It has been implemented using an IDDQ testable microprocessor (the Intel386TM EX embedded microprocessor) and an off-chip current senso...
 
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments
Found in: VLSI Test Symposium, IEEE
By I. de Paúl, M. Rosales, B. Alorda, J. Segura, C. Hawkins, J. Soden
Issue Date:April 2001
pp. 0286
We evaluated a diagnostic technique based on the charge delivered to the IC during a transition. Charge computed from the transient supply current is related to the circuit internal activity. A specific activity can be forced into the circuit using appropr...
 
A BIST-based Charge Analysis for Embedded Memories
Found in: On-Line Testing Symposium, IEEE International
By B. Alorda, V. Canals, I. de Paúl, J. Segura
Issue Date:July 2004
pp. 199
We present a BIST architecture to perform Charge Based Analysis on embedded memories. The architecture includes a charge monitor as well as the input generation and output processing circuitry. The method applies a charge correlation technique validated ex...
 
A BICS for CMOS Opamps by Monitoring the Supply Current Peak
Found in: On-Line Testing Workshop, IEEE International
By J. Font, J. Ginard, E. Isern, M. Roca, J. Segura, E. García
Issue Date:July 2002
pp. 94
We present a Built-In-Current-Sensor (BICS) based on monitoring the supply current peak of CMOS opamps using the oscillation-test-strategy. The BICS takes a weighed sample of the current through each opamp current branch and monitors the peak value under o...
 
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits
Found in: On-Line Testing Symposium, IEEE International
By B. Alorda, S. Bota, J. Segura
Issue Date:July 2005
pp. 177-182
We propose and evaluate a non-intrusive built-in monitor oriented to transient current based testing of digital CMOS VLSI circuits. The monitor measures the transient current idd(t) by sensing the voltage drop at an inductance coupled to the magnetic field...
 
Analyzing the Need for ATPG Targeting GOS Defects
Found in: VLSI Test Symposium, IEEE
By E. Isern, M. Roca, J. Segura
Issue Date:April 1999
pp. 420
In this work the need for specific ATPG targeting Gate Oxide Short (GOS) defects is highlighted. Many works have been done to develop ATPG for resistive shorts considering both external bridges between gates, and intra-gate shorts. We show with some exampl...
 
On the Influence of Frame-Asynchronous Grammar Scoring in a CSR System
Found in: Acoustics, Speech, and Signal Processing, IEEE International Conference on
By A. Rubio, J. Diaz, P. Garcia, J. Segura
Issue Date:April 1997
pp. 895
No summary available.
 
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories
Found in: On-Line Testing Symposium, IEEE International
By S. A. Bota, G. Torrens, B. Alorda, J. Verd, J. Segura
Issue Date:July 2010
pp. 141-146
Error correction codes combined with built-in current sensors (BICS) have been proposed as an effective technique to detect and correct SEU errors in memories. As technology scales down, multiple bit upsets affecting the same word are becoming more common ...
 
WITHIN DIE THERMAL GRADIENT IMPACT ON CLOCK-SKEW: ANEW TYPE OF DELAY-FAULT MECHANISM
Found in: Test Conference, International
By S.A. Bota, M. Rosales, J.L. Rosello, J. Segura, A. Keshavarzi
Issue Date:October 2004
pp. 1276-1284
As chips become faster, the need to test them at their intended speed of operation has been recognized. High-speed operation, together with the higher switching activity typically induced during test, can result in a die-thermal distribution significantly ...
 
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J. L. Rosselló, V. Canals, S. A. Bota, A. Keshavarzi, J. Segura
Issue Date:March 2005
pp. 206-211
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue ...
 
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing
Found in: On-Line Testing Symposium, IEEE International
By B. Alorda, J. Segura
Issue Date:July 2003
pp. 178
We evaluate the possibilities of transient current testing practical implementation by comparing the transient supply current signature at the external circuit supply pins to its internal behavior. To do this we develop and analyze a hierarchical power-gri...
 
GHz Testing and Its Fuzzy Targets
Found in: Test Conference, International
By C. Hawkins, J. Segura
Issue Date:October 2002
pp. 1228
No summary available.
   
A built-in quiescent current monitor for CMOS VLSI circuits
Found in: European Design and Test Conference
By A. Rubio, E. Janssens, H. Casier, J. Figueras, D. Mateo, P. De Pauw, J. Segura
Issue Date:March 1995
pp. 581
A built-in I/sub DDQ/ monitor for CMOS digital circuits with low power supply voltage perturbation is presented. It minimizes the extra delay of the CUT in normal operation. An automatic recovery mechanism limits the drop in VDD voltage during the testing ...
 
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation
Found in: 2011 Design, Automation & Test in Europe
By B Alorda,G Torrens,S Bota,J Segura
Issue Date:March 2011
pp. 1-6
SRAM cell stability analysis is typically based on Static Noise Margin (SNM) evaluation when in hold mode, although memory errors may also occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode...
   
A compact model to identify delay faults due to crosstalk
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J.L. Rossello, J. Segura
Issue Date:March 2006
pp. 192
In this work we present an analytical formulation to estimate quickly and accurately the impact of crosstalk induced delay in submicron CMOS ICs gates taking into account time skew. Crosstalk delay is computed from the additional charge injected from the a...
 
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk
Found in: Design, Automation and Test in Europe Conference and Exhibition
By J. L. Rosselló, J. Segura
Issue Date:February 2004
pp. 20954
We present a compact, fully physical, analytical model for the propagation delay and the output transition time of deep-submicron CMOS gates. The model accounts for crosstalk effects, short-circuit currents, the input-output coupling capacitance and carrie...
 
Charge Based Testing (CBT) of submicron CMOS SRAMs
Found in: Defect Based Testing, IEEE International Workshop on
By M. Rosales, I. de Paúl, J. Segura, C. F. Hawkins, J. Soden
Issue Date:April 2000
pp. 57
A transient current testing technique that computes the charge delivered to the circuit during the transient circuit operations is analyzed. The method is applied to 0.5 ?m CMOS SRAMs with 1.5 million transistors that passed various logic test. Results sho...
 
Transient Current Testing Based on Current (Charge) Integration
Found in: IDDQ Testing, IEEE International Workshop on
By I. de Paúl, R. Picos, J.L. Rosselló, M. Roca, E. Isern, J. Segura, C.F. Hawkins
Issue Date:November 1998
pp. 26
We evaluated a technique that uses power supply charge as the test observable. Charge was computed from the measured supply transient current waveform. Data show that this method is efficient to detect those defects that prevent current elevation (mainly
 
Integrated Cmos Linear Dosimeter
Found in: Integrated Circuit Design and System Design, Symposium on
By O. Calvo, M. González, C. Romero, E. García-Moreno, E. Isern, M. Roca, J. Segura
Issue Date:February 1998
pp. 78
This paper presents a review of radiation sensors; their basic principles and a possible use as built-in sensors in Integrated Circuits exposed to ionizing radiation. Two radiation dosimeters are discussed: threshold and linear. All are CMOS circuits compa...
 
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment
Found in: On-Line Testing Symposium, IEEE International
By X. Cano, S. Bota, R. Graciani, D. Gascón, A. Herms, A. Comerma, J. Segura, L. Garrido
Issue Date:July 2007
pp. 183-184
A heavy ion radiation test has been performed to evaluate the SEU sensitivity on a mixed-mode ASIC. We present the results obtained when the Triple Voting Registers used in the digital block of the ASIC are irradiated with heavy ions.
   
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?
Found in: VLSI Test Symposium, IEEE
By S.A. Bota,, M. Rosales, J.L. Rosselló, J. Segura
Issue Date:May 2006
pp. 358-363
Delay testing at low-V_D_D has been proposed as a useful test method to expose delay defects not detectable at nominal supply voltages. The advantage of this technique comes from the reduced transistor strength at lower supply voltages that increases the i...
 
An Off-Chip Sensor Circuit for On-Line Transient Current Testing
Found in: On-Line Testing Workshop, IEEE International
By B. Alorda, A. Ivanov, J. Segura
Issue Date:July 2002
pp. 192
No summary available.
   
Experimental Results on BIC Sensors for Transient Current Testing
Found in: European Test Workshop, IEEE
By R. Picos, M. Roca, E. Isern, J. Segura, E. García-Moreno
Issue Date:September 1999
pp. 46
In this work experimental results on a built in current sensor for dynamic current testing, IDDT, based on integration concepts are presented. The experimental validation proposed in this work is done through a VLSI CMOS circuit implemented in a 0.7 micron...
 
Reliability Analysis of Small Delay Defects Due to Via Narrowing in Signal Paths
Found in: IEEE Design & Test of Computers
By H. VILLACORTA,V. Champac,R. Gomez,C. Hawkins,J. Segura
Issue Date:January 2013
pp. 1
Open defects in vias are a dominant failure mechanism in nanometer technologies. Their defect probability has increased with the introduction of the copper process, smaller geometries, and via counts on the order of billions for modern integrated circuits....
 
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation
Found in: 2011 Design, Automation & Test in Europe
By S Barceló,X Gili,Sebastià Bota,J Segura
Issue Date:March 2011
pp. 1-6
We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit We also report ...
   
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