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Displaying 1-11 out of 11 total
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. Freijedo, J. J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:April 2007
pp. 1-6
As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology t...
 
Signal Integrity Enhancement in Digital Circuits
Found in: IEEE Design & Test of Computers
By Jorge Filipe L C Semia̅o,Leonardo Bisch Piccoli,Fabian Luis Vargas,Marcial Jesus Rodriguez Irago,Juan J Rodriguez-Andina,Marcelino Bicho dos Santos,Isabel Maria Cacho Teixeira,Joao Paulo Teixeira
Issue Date:September 2008
pp. 452-461
This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay var...
 
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By J. Semião, J. J. Rodríguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:September 2007
pp. 303-311
A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. In the prop...
 
Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection
Found in: Digital Systems Design, Euromicro Symposium on
By Lucía Costas, Juan J. Rodríguez-Andina
Issue Date:September 2005
pp. 64-71
<p>This paper presents a methodology for characterizing the behaviour of wavelet-based image coding systems in the presence of faults. This is a previous step in the development of efficient concurrent error detection techniques for such systems. The...
 
Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems
Found in: IEEE Design and Test of Computers
By Lucía Costas-Pérez, Juan J. Rodríguez-Andina
Issue Date:January 2009
pp. 60-67
Fault tolerance capabilities are becoming a fundamental requirement in many designs. Improving these systems' dependability under demanding environmental and operating conditions requires new techniques that use concurrent error detection (CED) strategies ...
 
High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic
Found in: Digital Systems Design, Euromicro Symposium on
By Miguel Pereira, Enrique Soto, Juan J. Rodríguez-Andina, F.Javier González-Castaño
Issue Date:September 2005
pp. 282-288
<p>High-speed telecommunications routers are very important systems in today?s networked environments. The purpose of this paper is to propose a mathematical model of the faulty behaviour of such systems and, derived from it, a scheme for the detecti...
 
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies
Found in: On-Line Testing Symposium, IEEE International
By J. Semiao, J. Freijedo, J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:June 2009
pp. 223-228
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-fau...
 
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:April 2008
pp. 1-4
This paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to V<inf>DD</inf> and temperature (T) instability, even in the presence of process var...
 
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects
Found in: Latin American Test Workshop
By M. Valdes,J. Freijedo,M. J. Moure,J. J. Rodriguez-Andina,J. Semiao,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-7
In current nanometer technologies, aging effects (due for instance to Negative Bias Thermal Instability) may appear after relatively short operating times, compared to the expected lifetime of circuits, even for relatively short-cycle consumer electronics....
 
Investigating the Use of BICS to detect resistive-open defects in SRAMs
Found in: On-Line Testing Symposium, IEEE International
By R. Chipana, L. Bolzani, F. Vargas, J. Semiao, J. Rodriguez-Andina, I. Teixeira, P. Teixeira
Issue Date:July 2010
pp. 200-201
Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused ...
 
Modeling the effect of process variations on the timing response of nanometer digital circuits
Found in: Latin American Test Workshop
By J. Freijedo,J. Semiao,J. J. Rodriguez-Andina,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-5
The implementation of complex, high-performance functionality in nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This p...
 
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