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Displaying 1-16 out of 16 total
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})
Found in: VLSI Test Symposium, IEEE
By H. Rahaman, J. Mathew, B.K. Sikdar, D.K. Pradhan
Issue Date:May 2007
pp. 422-430
This paper presents a C-testable technique for detecting transition faults with 100% fault coverage in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2^{m}). The proposed technique requires only 10 vectors, which is independent of ...
 
Multiple Bit Error Detection and Correction in GF Arithmetic Circuits
Found in: Electronic System Design, International Symposium on
By J. Mathew, S. Banerjee, P. Mahesh, D. K. Pradhan, A. M. Jabir, S. P. Mohanty
Issue Date:December 2010
pp. 101-106
This paper presents a design technique for multiple bit error correctable (fault tolerant) polynomial basis (PB) multipliers over GF(2^m). These multipliers are the building blocks in certain types of cryptographic hardware, e.g. the Elliptic Curve Crypto ...
 
A Galois Field Based Logic Synthesis Approach with Testability
Found in: VLSI Design, International Conference on
By J. Mathew, H. Rahaman, A.K Singh, A.M. Jabir, D.K Pradhan
Issue Date:January 2008
pp. 629-634
of the most demanding requirements. Efficient testable logic synthesis is one way to tackle the problem. To this end, this paper introduces a new fast efficient graph-based decomposition technique for Boolean functions in finite fields, which utilizes the ...
 
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)
Found in: High-Level Design, Validation, and Test Workshop, IEEE International
By H. Rahaman, J. Mathew, A.M. Jabir, D.K. Pradhan
Issue Date:November 2006
pp. 48-54
A testable implementation of bit parallel multiplier over the finite field GF(2<sup>m</sup>) is proposed. A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2<sup>m</sup>) m...
 
Single Event Upset Detection and Correction
Found in: Information Technology, International Conference on
By Jawar Singh, J. Mathew, M. Hosseinabady, D. K. Pradhan
Issue Date:December 2007
pp. 13-18
This paper proposes a low cost solution to detect and correct a transient faults in registers of a design. The proposed method realizes a single- event upset detection and correction (SEU-DC) technique. The detection and correction of SEU in registers of a...
 
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set
Found in: On-Line Testing Symposium, IEEE International
By J. Mathew, H. Rahaman, D.K. Pradhan
Issue Date:July 2007
pp. 207-208
We present a C-testable method for detecting stuck-at (s-a) faults in the polynomial basis (PB) bit parallel multiplier circuits over GF(2m). It requires only 7 tests for detecting faults to provide 100% fault coverage, which is independent of the multipli...
   
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)
Found in: VLSI Design, International Conference on
By H. Rahaman, J. Mathew, D. K. Pradhan
Issue Date:January 2007
pp. 479-484
In this paper, a C-testable implementation of polynomial basis (PB) bit parallel (BP) multiplier over the Galois fields of form GF(2m) for detecting stuck-at faults in multiplier circuits has been proposed. The length of the constant test set is only 8. Th...
 
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization
Found in: VLSI Design, International Conference on
By S. Banerjee, J. Mathew, D.K. Pradhan, S.P. Mohanty, M. Ciesielski
Issue Date:January 2011
pp. 304-309
As technology scales down to nanometer regime the process variations have profound effect on circuit characteristics. Meeting timing and power constraints under such process variations in nano-CMOS circuit design is increasingly difficult. This causes a sh...
 
A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization
Found in: Electronic System Design, International Symposium on
By S. Banerjee, J. Mathew, D. K. Pradhan, S. P. Mohanty, M. Ciesielski
Issue Date:December 2010
pp. 71-76
Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano − CMOS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage cur...
 
C-testable S-box implementation for secure advanced encryption standard
Found in: On-Line Testing Symposium, IEEE International
By H. Rahaman, J. Mathew, A. Jabir, D. K. Pradhan
Issue Date:June 2009
pp. 210-211
We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overh...
 
Low-power design strategies for mobile computing
Found in: Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design
By A.V.S.S. Prasad,J. Mathews,N. Naganathan
Issue Date:July 2014
pp. 2 pp.
Summary form only for tutorial. The advent of nanometer design process has enabled the integration of multi-million gates with a variety of functionality as a system-on-chip (SoC). The demand for high levels of integration in SoCs are fueled by a strong de...
   
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies
Found in: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
By M. Poolakkaparambil,J. Mathew,A.M. Jabir,S.P. Mohanty
Issue Date:August 2012
pp. 141-146
Permanent and temporary transient faults are the main concern in modern very large scale integrated circuits (VLSI). The main reason for such high vulnerability of the modern integrated circuit is their high integration density. Miniaturization of devices ...
 
An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m)
Found in: Computer-Aided Design, International Conference on
By A.M. Jabir, D.K. Pradhan, J. Mathew
Issue Date:November 2006
pp. 151-157
This paper presents an efficient technique for synthesis and optimization of polynomials over GF(2<sup>m</sup>), where mis a non-zero positive integer. The technique is based on a graph-based decomposition and factorization of polynomials over ...
 
Work in Progress: Assessing Student Acquisition of Knowledge of Learning Objectives for an Interprofessional Projects Program
Found in: Frontiers in Education, Annual
By J. Mathews,D. Ferguson,M. Huyek,A. Pamulaparthy
Issue Date:October 2006
pp. 7-8
The Interprofessional Projects Program (IPROreg) at our university provides a multi-disciplinary, project team based course required of all undergraduates which helps develop in these students various knowledge and skills deemed essential by ABET and futur...
 
Development routes for message passing parallelism in Java
Found in: Proceedings of the ACM 2000 conference on Java Grande (JAVA '00)
By H. A. James, J. A. Mathew, K. A. Hawick
Issue Date:June 2000
pp. 54-61
The Stock Tracker is a personalized recommendation system for trading stocks. The system tailors its buy, sell, and hold recommendations to individual users through automatically acquired content-based models of user preferences. It relies on data gathered...
     
Analysis and development of Java Grande benchmarks
Found in: Proceedings of the ACM 1999 conference on Java Grande (JAVA '99)
By J. A. Mathew, K. A. Hawick, P. D. Coddington
Issue Date:June 1999
pp. 72-80
The Stock Tracker is a personalized recommendation system for trading stocks. The system tailors its buy, sell, and hold recommendations to individual users through automatically acquired content-based models of user preferences. It relies on data gathered...
     
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