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Displaying 1-7 out of 7 total
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
Found in: Design and Diagnostics of Electronic Circuits and Systems
By J. Semiao, J. Freijedo, J. J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:April 2007
pp. 1-6
As IC technology scales down, power supply voltage and temperature variations play an increasing role in signal integrity loss, which lead to performance degradation, reliability problems and functional errors. In this paper, we propose a new methodology t...
 
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects
Found in: Latin American Test Workshop
By M. Valdes,J. Freijedo,M. J. Moure,J. J. Rodriguez-Andina,J. Semiao,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-7
In current nanometer technologies, aging effects (due for instance to Negative Bias Thermal Instability) may appear after relatively short operating times, compared to the expected lifetime of circuits, even for relatively short-cycle consumer electronics....
 
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies
Found in: On-Line Testing Symposium, IEEE International
By J. Semiao, J. Freijedo, J. Rodriguez-Andina, F. Vargas, M. Santos, I. Teixeira, P. Teixeira
Issue Date:June 2009
pp. 223-228
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-fau...
 
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By J. Semião, J. Freijedo, J.J. Rodríguez-Andina, F. Vargas, M.B. Santos, I.C. Teixeira, J.P. Teixeira
Issue Date:July 2007
pp. 167-172
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (VDD) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional ...
 
Modeling the effect of process variations on the timing response of nanometer digital circuits
Found in: Latin American Test Workshop
By J. Freijedo,J. Semiao,J. J. Rodriguez-Andina,F. Vargas,I. C. Teixeira,J. P. Teixeira
Issue Date:March 2011
pp. 1-5
The implementation of complex, high-performance functionality in nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This p...
 
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits
Found in: VLSI, IEEE Computer Society Annual Symposium on
By J. Semiao, J. Freijedo, J.J. Rodríguez Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Issue Date:March 2007
pp. 207-212
As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, we propose a new methodology to enhance circuit tolerance to powersupply voltage (VDD) local variations, without degrading its perfo...
 
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs
Found in: International Conference on Field Programmable Logic and Applications
By V. Bexiga,C. Leong,J. Semião,I.C. Teixeira,J.P. Teixeira,M. Valdés,J. Freijedo,J.J. Rodríguez-Andina,F. Vargas
Issue Date:September 2011
pp. 301-304
The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval...
 
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