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Displaying 1-6 out of 6 total
Towards improved survivability in safety-critical systems
Found in: On-Line Testing Symposium, IEEE International
By J. Abella,F. J. Cazorla,E. Quinones,Dimitris Gizopoulos,Arnaud Grasset,Sami Yehia,Philippe Bonnot,R. Mariani,G. Bernat
Issue Date:July 2011
pp. 240-245
Performance demand of Critical Real-Time Embedded (CRTE) systems implementing safety-related system features grows at an exponential rate. Only modern semiconductor technologies can satisfy CRTE systems performance needs efficiently. However, those technol...
 
Online error detection and correction of erratic bits in register files
Found in: On-Line Testing Symposium, IEEE International
By X. Vera, J. Abella, J. Carretero, P. Chaparro, A. Gonzalez
Issue Date:June 2009
pp. 81-86
Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient gate leakage (a trap in the gate ox...
 
parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By T. Ungerer,C. Bradatsch,M. Gerdes,F. Kluge,R. Jahr,J. Mische,J. Fernandes,P.G. Zaykov,Z. Petrov,B. Boddeker,S. Kehr,H. Regler,A. Hugl,C. Rochange,H. Ozaktas,H. Casse,A. Bonenfant,P. Sainrat,I. Broster,N. Lay,D. George,E. Quinones,M. Panic,J. Abella,F. Cazorla,S. Uhrig,M. Rohde,A. Pyka
Issue Date:September 2013
pp. 363-370
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and runnin...
 
RVC-based time-predictable faulty caches for safety-critical systems
Found in: On-Line Testing Symposium, IEEE International
By J. Abella,E. QuiƱones,F. J. Cazorla,M. Valero,Y. Sazeides
Issue Date:July 2011
pp. 25-30
Technology and Vcc scaling lead to significant faulty bit rates in caches. Mechanisms based on disabling faulty parts show to be effective for average performance but are unacceptable in safety critical systems where worst-case execution time (WCET) estima...
 
parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
Found in: 2013 Euromicro Conference on Digital System Design (DSD)
By T. Ungerer,C. Bradatsch,M. Gerdes,F. Kluge,R. Jahr,J. Mische,J. Fernandes,P.G. Zaykov,Z. Petrov,B. Boddeker,S. Kehr,H. Regler,A. Hugl,C. Rochange,H. Ozaktas,H. Casse,A. Bonenfant,P. Sainrat,I. Broster,N. Lay,D. George,E. Quinones,M. Panic,J. Abella,F. Cazorla,S. Uhrig,M. Rohde,A. Pyka
Issue Date:September 2013
pp. 363-370
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and runnin...
 
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
Found in: Parallel and Distributed Processing Symposium, International
By J. Abella,A. Gonzalez
Issue Date:April 2006
pp. 33
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots. This paper presents a highly banked, set-associative, multiple-in...
 
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