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Displaying 1-14 out of 14 total
Minimizing Delay in Shared Pipelines
Found in: 2013 IEEE 21st Annual Symposium on High-Performance Interconnects (HOTI)
By Ori Rottenstreich,Isaac Keslassy,Yoram Revah,Aviran Kadosh
Issue Date:August 2013
pp. 9-16
Pipelines are widely used to increase throughput in multi-core chips by parallelizing packet processing. Typically, each packet type is serviced by a dedicated pipeline. However, with the increase in the number of packet types and their number of required ...
 
Optimal Resource Allocation with MultiAmdahl
Found in: Computer
By Tsahee Zidenberg,Isaac Keslassy,Uri Weiser
Issue Date:July 2013
pp. 70-77
The MultiAmdahl framework provides an optimal resource allocation in heterogeneous multiprocessor chips, given a model of the workload and of the performance of each on-chip component.
 
MultiAmdahl: How Should I Divide My Heterogenous Chip?
Found in: IEEE Computer Architecture Letters
By Tsahee Zidenberg,Isaac Keslassy,Uri Weiser
Issue Date:July 2012
pp. 65-68
Future multiprocessor chips will integrate many different units, each tailored to a specific computation. When designing such a system, a chip architect must decide how to distribute the available limited system resources, such as area and power, among all...
 
Packet-level static timing analysis for NoCs
Found in: Networks-on-Chip, International Symposium on
By Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter
Issue Date:May 2009
pp. 88
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors, increasing the need for accurate and efficient modeling to aid the design of these highly-integrated systems. Towards this modeling goal, we present a methodology for p...
 
Statistical Approach to NoC Design
Found in: Networks-on-Chip, International Symposium on
By Itamar Cohen, Ori Rottenstreich, Isaac Keslassy
Issue Date:April 2008
pp. 171-180
Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability ...
 
A Scalable Switch for Service Guarantees
Found in: High-Performance Interconnects, Symposium on
By Bill Lin, Isaac Keslassy
Issue Date:August 2005
pp. 93-99
<p>Operators need routers to provide service guarantees such as guaranteed flow rates and fairness among flows, so as to support real-time traffic and traffic engineering. However, current centralized input-queued router architectures cannot scale to...
 
The Switch Reordering Contagion: Preventing a Few Late Packets from Ruining the Whole Party
Found in: IEEE Transactions on Computers
By Ori Rottenstreich,Pu Li,Inbal Horev,Isaac Keslassy,Shivkumar Kalyanaraman
Issue Date:May 2014
pp. 1262-1276
Packet reordering has now become one of the most significant bottlenecks in next-generation switch designs. A switch practically experiences a reordering delay contagion, such that a few late packets may affect a disproportionate number of other packets. T...
 
Statistical Approach to Networks-on-Chip
Found in: IEEE Transactions on Computers
By Itamar Cohen, Ori Rottenstreich, Isaac Keslassy
Issue Date:June 2010
pp. 748-761
Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability ...
 
Using Hardware to Configure a Load-Balanced Switch
Found in: IEEE Micro
By Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy, Nick McKeown
Issue Date:January 2005
pp. 70-78
The load-balanced switch is a promising way to scale router capacity. In this 100-terabit-per-second router, an optical switch spreads traffic evenly among linecards. When the network operator adds or removes linecards, reconfiguring the switch can be time...
 
Maximizing the Throughput of Hash Tables in Network Devices with Combined SRAM/DRAM Memory
Found in: IEEE Transactions on Parallel and Distributed Systems
By Yossi Kanizo,David Hay,Isaac Keslassy
Issue Date:April 2014
pp. 1
Hash tables form a core component of many algorithms as well as network devices. Because of their large size, they often require a combined memory model, in which some of the elements are stored in a fast memory (for example, cache or on-chip SRAM) while o...
 
On the Capacity of Bufferless Networks-on-Chip
Found in: IEEE Transactions on Parallel and Distributed Systems
By Alexander Shpiner,Erez Kantor,Pu Li,Israel Cidon,Isaac Keslassy
Issue Date:March 2014
pp. 1
Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, ...
 
Distributed adaptive routing for big-data applications running on data center networks
Found in: Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems (ANCS '12)
By Avinoam Kolodny, Eitan Zahavi, Isaac Keslassy
Issue Date:October 2012
pp. 99-110
With the growing popularity of big-data applications, Data Center Networks increasingly carry larger and longer traffic flows. As a result of this increased flow granularity, static routing cannot efficiently load-balance traffic, resulting in an increased...
     
Packet-mode emulation of output-queued switches
Found in: Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures (SPAA '06)
By David Hay, Hagit Attiya, Isaac Keslassy
Issue Date:July 2006
pp. 138-147
Most common network protocols (e.g., the Internet Protocol) work with variable size packets, whereas contemporary switches still operate with fixed size cells, which are easier to transmit and buffer. This necessitates packet segmentation and reassembly mo...
     
Sizing router buffers
Found in: Proceedings of the 2004 conference on Applications, technologies, architectures, and protocols for computer communications (SIGCOMM '04)
By Guido Appenzeller, Isaac Keslassy, Nick McKeown
Issue Date:August 2004
pp. 95-104
All Internet routers contain buffers to hold packets during times of congestion. Today, the size of the buffers is determined by the dynamics of TCP's congestion control algorithm. In particular, the goal is to make sure that when a link is congested, it i...
     
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