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Displaying 1-50 out of 74 total
A Hybrid Scheme for Concurrent Error Detection of Multiplication over Finite Fields
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Bijan Ansari, Ingrid Verbauwhede
Issue Date:October 2010
pp. 399-407
Concurrent error detection (CED) schemes for finite field multipliers over GF(2m), based on simple parity bits, have been proposed in the literature. In this paper, we generalize the concept of parity and derive a hybrid scheme for CED. We extend the one-b...
 
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
Issue Date:September 2006
pp. 15-18
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor platform spans multiple design layers, including the application layer, the syste...
   
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
Issue Date:September 2006
pp. 354-359
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this bound. According to the results of FPGA implementations, 3,541 Mbps with a pipeli...
 
Securing Embedded Systems
Found in: IEEE Security and Privacy
By David D. Hwang, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
Issue Date:March 2006
pp. 40-49
A top-down, multiabstraction layer approach for embedded security design reduces the risk of security flaws, letting designers maximize security while limiting area, energy, and computation costs.
 
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System
Found in: Computer Design, International Conference on
By Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
Issue Date:October 2005
pp. 102-104
<p>Multiprocessor systems offer superior performance and potentially better energy-reduction than single-processor systems. It all depends however, on how well the application can be mapped onto the architecture. Indeed, a careful tradeoff of energy ...
   
Microcoded coprocessor for embedded secure biometric authentication systems
Found in: Hardware/software codesign and system synthesis, International conference on
By Ingrid Verbauwhede, Patrick Schaumont, Shenglin Yang
Issue Date:September 2005
pp. 130-135
We design and implement a cryptographic biometric authentication system using a microcoded architecture. The secure properties of the biometric matching process are obtained by means of a fuzzy vault scheme. The algorithm is implemented in a reprogrammable...
 
A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks
Found in: Information Technology: Coding and Computing, International Conference on
By Alireza Hodjat, David D. Hwang, Ingrid Verbauwhede
Issue Date:April 2005
pp. 538-543
This paper presents a high performance and scalable elliptic curve processor which is designed to be resistant against timing attacks. The point multiplication algorithm (double-add-subtract) is modified so that the processor performs the same operations f...
 
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Kris Tiri, Ingrid Verbauwhede
Issue Date:March 2005
pp. 58-63
This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a...
 
Design Method for Constant Power Consumption of Differential Logic Circuits
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Kris Tiri, Ingrid Verbauwhede
Issue Date:March 2005
pp. 628-633
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue,...
 
Reducing Radio Energy Consumption of Key Management Protocols for Wireless Sensor Networks
Found in: Low Power Electronics and Design, International Symposium on
By Bo-Cheng Charles Lai, David D. Hwang, Sungha Pete Kim, Ingrid Verbauwhede
Issue Date:August 2004
pp. 351-356
The security of sensor networks is a challenging area. Key management is one of the crucial parts in constructing the security among sensor nodes. However, key management protocols require a great deal of energy consumption, particularly in the transmissio...
 
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
Found in: Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
By Alireza Hodjat, Ingrid Verbauwhede
Issue Date:April 2004
pp. 308-309
This paper presents the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining techniques, a maximum throughput of 21.54 Gbits/s is achieved. A fast and area effi...
   
Integrated Modeling and Generation of a Reconfigurable Network-on-Chip
Found in: Parallel and Distributed Processing Symposium, International
By Doris Ching, Patrick Schaumont, Ingrid Verbauwhede
Issue Date:April 2004
pp. 139b
While a communication network is a critical component for an efficient system-on-chip multiprocessor, there are few approaches available to help with system-level architectural exploration of such a specialized interconnection network. This paper presents ...
 
Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network
Found in: Information Technology: Coding and Computing, International Conference on
By Herwin Chan, Alireza Hodjat, Jun Shi, Richard Wesel, Ingrid Verbauwhede
Issue Date:April 2004
pp. 578
This paper describes a working implementation of a streaming encryption system for optical networks. The 10 Gbps data stream is encrypted on the physical level in both the wavelength and time domains. Security is obtained by applying a strong pseudo-random...
 
Architectural Design Features of a Programmable High Throughput AES Coprocessor
Found in: Information Technology: Coding and Computing, International Conference on
By Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede
Issue Date:April 2004
pp. 498
Programmable, high throughput domain specific crypto processors are required for different networking applications. This paper presents the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domai...
 
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
Issue Date:February 2004
pp. 20988
<p>Energy efficient embedded systems consist of a heterogeneous collection of very specific building blocks, connected together by a complex network of many dedicated busses and interconnect options. The trend to merge multiple functions into one dev...
 
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor
Found in: VLSI, IEEE Computer Society Annual Symposium on
By Alireza Hodjat, Ingrid Verbauwhede
Issue Date:February 2004
pp. 83
This paper presents the design decisions and area optimizations to obtain a high throughput, over 30 Gbits/s AES processor. With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18 µm CMOS ...
 
Interactive Cosimulation with Partial Evaluation
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Patrick Schaumont, Ingrid Verbauwhede
Issue Date:February 2004
pp. 10642
<p>We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimization is partial evaluation. Our contribution is that we apply the optim...
 
Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System
Found in: Design Automation Conference
By David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede
Issue Date:June 2003
pp. 60
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents the concept of HW/SW acceleration transparency, a systematic method to acceler...
 
Domain-Specific Codesign for Embedded Security
Found in: Computer
By Patrick Schaumont, Ingrid Verbauwhede
Issue Date:April 2003
pp. 68-74
<p>Systems with multiple design domains require codesign of application domains. Dedicated hardware processors implement the application domains and software integrates them. </p><p>The authors use ThumbPod, a proto-type embedded security...
 
BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor
Found in: IEEE Transactions on Computers
By Santosh Ghosh,Ingrid Verbauwhede
Issue Date:May 2014
pp. 1124-1133
This paper presents a 128-bit CCA2-secure McEliece cryptoprocessor. The existing side-channel vulnerabilities in this regard are also taken care during the implementation of such a post-quantum immune code-based cryptosystem. In order to achieve CCA2 secur...
 
SPONGENT: The Design Space of Lightweight Cryptographic Hashing
Found in: IEEE Transactions on Computers
By Andrey Bogdanov,Miroslav Knezevic,Gregor Leander,Deniz Toz,Kerem Varici,Ingrid Verbauwhede
Issue Date:October 2013
pp. 2041-2053
The design of secure yet efficiently implementable cryptographic algorithms is a fundamental problem of cryptography. Lately, lightweight cryptography--optimizing the algorithms to fit the most constrained environments--has received a great deal of attenti...
 
A Speed Area Optimized Embedded Co-processor for McEliece Cryptosystem
Found in: 2012 IEEE 23rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)
By Santosh Ghosh,Jeroen Delvaux,Leif Uhsadel,Ingrid Verbauwhede
Issue Date:July 2012
pp. 102-108
This paper describes the systematic design methods of an embedded co-processor for a post quantum secure McEliece cryptosystem. A hardware/software co-design has been  targeted for the realization of McEliece in practice on low-cost embedded platforms. Des...
 
Interface Design for Mapping a Variety of RSA Exponentiation Algorithms on a HW/SW Co-design Platform
Found in: 2012 IEEE 23rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)
By Leif Uhsadel,Markus Ullrich,Ingrid Verbauwhede,Bart Preneel
Issue Date:July 2012
pp. 109-116
When mapping public-key algorithms, such as RSA, onto constrained devices, both efficiency and flexibility are a challenge. Because word lengths are large, minimum 1024 bits, typically a dedicated co-processor is used. On the other hand, flexibility is req...
 
The Fault Attack Jungle - A Classification Model to Guide You
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Ingrid Verbauwhede,Duško Karaklajic,Jörn-Marc Schmidt
Issue Date:September 2011
pp. 3-8
For a secure hardware designer, the vast array of fault attacks and countermeasures looks like a jungle. This paper aims at providing a guide through this jungle and at helping a designer of secure embedded devices to protect a design in the most efficient...
 
An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Josep Balasch,Benedikt Gierlichs,Ingrid Verbauwhede
Issue Date:September 2011
pp. 105-114
The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on some assumed fault model. Our work narrows the gap between both topics. We thoroughly anal...
 
Efficient Hardware Implementation of Fp-Arithmetic for Pairing-Friendly Curves
Found in: IEEE Transactions on Computers
By Junfeng Fan,Frederik Vercauteren,Ingrid Verbauwhede
Issue Date:May 2012
pp. 676-685
This paper describes a new method to speed up {\hbox{\rlap{I}\kern 2.0pt{\hbox{F}}}}_p-arithmetic in hardware for pairing-friendly curves, such as the well-known Barreto-Naehrig (BN) curves. We explore the characteristics of the modulus defined by these cu...
 
Low Cost Built in Self Test for Public Key Crypto Cores
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Duško Karaklajic, Miroslav Kneževic, Ingrid Verbauwhede
Issue Date:August 2010
pp. 97-103
The testability of cryptographic cores brings an extra dimension to the process of digital circuits testing security. The benefits of the classical methods such as the scan-chain method introduce new vulnerabilities concerning the data protection. The Buil...
 
Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware
Found in: International Conference on Field Programmable Logic and Applications
By Junfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Güneysu, Christof Paar, Ingrid Verbauwhede
Issue Date:September 2010
pp. 133-138
This paper reports a new speed record for FPGAs in cracking Elliptic Curve Cryptosystems. We conduct a detailed analysis of different $\textbf{F}_{2^m}$ multiplication approaches in this application. A novel architecture using optimized normal basis multip...
 
Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods
Found in: IEEE Transactions on Computers
By Miroslav Knežević, Frederik Vercauteren, Ingrid Verbauwhede
Issue Date:December 2010
pp. 1715-1721
This paper proposes two improved interleaved modular multiplication algorithms based on Barrett and Montgomery modular reduction. The algorithms are simple and especially suitable for hardware implementations. Four large sets of moduli for which the propos...
 
Analysis and design of active IC metering schemes
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Roel Maes, Dries Schellekens, Pim Tuyls, Ingrid Verbauwhede
Issue Date:July 2009
pp. 74-81
Outsourcing the fabrication of semiconductor devices to merchant foundries raises some issues concerning the IP protection of the design. Active hardware metering schemes try to counter piracy of integrated circuits by enforcing the fabrication plant to ru...
 
FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags
Found in: On-Line Testing Symposium, IEEE International
By Junfeng Fan, Miroslav Knezevic, Dusko Karaklajic, Roel Maes, Vladimir Rozic, Lejla Batina, Ingrid Verbauwhede
Issue Date:June 2009
pp. 189-191
Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, an...
 
Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors
Found in: Security and Privacy, IEEE Symposium on
By Bart Coppens, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter
Issue Date:May 2009
pp. 45-60
This paper studies and evaluates the extent to which automated compiler techniques can defend against timing-based side-channel attacks on modern x86 processors. We study how modern x86 processors can leak timing information through side-channels that rela...
 
Case Study : A class E power amplifier for ISO-14443A
Found in: Design and Diagnostics of Electronic Circuits and Systems
By Elke De Mulder, Wim Aerts, Bart Preneel, Ingrid Verbauwhede, Guy Vandenbosch
Issue Date:April 2009
pp. 20-23
This paper reports on the design and implementation of a class E push-pull amplifier in order to increase the reading range of an ISO-14443A RFID system. With the aid of classical design formulas and some alterations due to parasitic and intrinsic capacita...
 
Elliptic-Curve-Based Security Processor for RFID
Found in: IEEE Transactions on Computers
By Yong Ki Lee, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede
Issue Date:November 2008
pp. 1514-1527
RFID (Radio Frequency IDentification) tags need to include security functions, yet at the same time their resources are extremely limited. Moreover, to provide privacy, authentication and protection against tracking of RFID tags without loosing the system ...
 
Exploiting Hardware Performance Counters
Found in: Fault Diagnosis and Tolerance in Cryptography, Workshop on
By Leif Uhsadel, Andy Georges, Ingrid Verbauwhede
Issue Date:August 2008
pp. 59-67
We introduce the usage of hardware performance counters (HPCs) as a new method that allows very precise access to known side channels and also allows access to many new side channels. Many current architectures provide hardware performance counters, which ...
 
Low-cost implementations of NTRU for pervasive security
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede, S. Berna Ors Yalcin
Issue Date:July 2008
pp. 79-84
NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design that is suitable for pervasive security applications such as RFIDs and sensor...
 
Extended abstract: Unified digit-serial multiplier/inverter in finite field GF(2<sup>m</sup>)
Found in: Hardware-Oriented Security and Trust, IEEE International Workshop on
By Junfeng Fan, Ingrid Verbauwhede
Issue Date:June 2008
pp. 72-75
Modular multiplication and inversion are the essential operations in both Elliptic Curve Cryptosystems (ECC) and HyperElliptic Curve Cryptosystems (HECC). In this paper, we describe a unified digit-serial multiplier/inverter in GF(2<sup>m</sup>...
 
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems
Found in: IEEE Transactions on Computers
By Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede
Issue Date:December 2008
pp. 1714-1719
This paper presents how a multi-core system can benefit from the use of a latency-aware memory bus capable of dual-concurrent data transfers on a single wire line: Source synchronous CDMA interconnect (SSCDMA-I) has been adopted to implement the memory bus...
 
FPGA Design for Algebraic Tori-Based Public-Key Cryptography
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid Verbauwhede
Issue Date:March 2008
pp. 1292-1297
Algebraic torus-based cryptosystems are an alternative for Public-Key Cryptography (PKC). It maintains the security of a larger group while the actual computations are performed in a subgroup. Compared with RSA for the same security level, it allows faster...
 
Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2^n)
Found in: IEEE Transactions on Computers
By Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
Issue Date:September 2007
pp. 1269-1282
This paper presents a reconfigurable curve-based cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GF(2<sup>n</sup>). By allocating &#x03B...
 
Multilevel Design Validation in a Secure Embedded System
Found in: IEEE Transactions on Computers
By Patrick Schaumont, David Hwang, Shenglin Yang, Ingrid Verbauwhede
Issue Date:November 2006
pp. 1380-1390
In this paper, we present the simulation-based validation approach that we used during the design of ThumbPod-2, a portable fingerprint authentication system. The particular nature of secure system design has considerable impact on the simulation requireme...
 
A Component-Based Design Environment for ESL Design
Found in: IEEE Design and Test of Computers
By Patrick Schaumont, Ingrid Verbauwhede
Issue Date:September 2006
pp. 338-347
This article focuses on two key properties that the authors see as critical to ESL design: abstraction and reuse. The authors present an ESL design flow using the Gezel language. Using several very different design examples, they show how this design flow ...
 
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
Found in: IEEE Transactions on Computers
By Alireza Hodjat, Ingrid Verbauwhede
Issue Date:April 2006
pp. 366-372
This paper explores the area-throughput trade-off for an ASIC implementation of the Advanced Encryption Standard (AES). Different pipelined implementations of the AES algorithm as well as the design decisions and the area optimizations that lead to a low a...
 
Side-Channel Leakage Tolerant Architectures
Found in: Information Technology: New Generations, Third International Conference on
By Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede
Issue Date:April 2006
pp. 204-209
Side-channel attacks compare side-channel leakage predictions or estimations with side-channel leakage measurements. The estimations are based on the exact value of a few select state bits. If it is impossible to calculate the value of the state bits, it i...
   
Side-Channel Issues for Designing Secure Hardware Implementations
Found in: On-Line Testing Symposium, IEEE International
By Lejla Batina, Nele Mentens, Ingrid Verbauwhede
Issue Date:July 2005
pp. 118-121
Selecting a strong cryptographic algorithm makes no sense if the information leaks out of the device through side-channels. Sensitive information, such as secret keys, can be obtained by observing the power consumption, the electromagnetic radiation, etc. ...
 
Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2^n )
Found in: Application-Specific Systems, Architectures and Processors, IEEE International Conference on
By Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede
Issue Date:July 2005
pp. 350-355
<p>This paper proposes efficient algorithms for Elliptic Curve Cryptography (ECC). As an example a compact and efficient FPGA architecture for ECC over finite fields of even characteristic is presented. The implementation is balanced in order to incr...
 
Embedded Software Integration for Coarse-Grain Reconfigurable Systems
Found in: Parallel and Distributed Processing Symposium, International
By Patrick Schaumont, Kazuo Sakiyama, Alireza Hodjat, Ingrid Verbauwhede
Issue Date:April 2004
pp. 137
<p>Coarse-grain reconfigurable systems offer high performance and energy-efficiency, provided an efficient run-time reconfiguration mechanism is available. Using an embedded software vantage point, we define three levels of reconfigurability for such...
 
High-Throughput Programmable Cryptocoprocessor
Found in: IEEE Micro
By Alireza Hodjat, Ingrid Verbauwhede
Issue Date:March 2004
pp. 34-45
A loosely coupled cryptocoprocessor based on the Advanced Encryption Standard combines high throughput with programmability. Using domain-specific instructions and design principles such as control hierarchy and block pipelining, the security engine suppor...
 
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Kris Tiri, Ingrid Verbauwhede
Issue Date:February 2004
pp. 10246
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks ...
 
Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients
Found in: Design Automation Conference
By Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Ingrid Verbauwhede, Georges Gielen, Hugo De Man
Issue Date:June 2002
pp. 399
In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the c...
 
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